Patents Examined by Thomas T Pham
  • Patent number: 12014935
    Abstract: The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: June 18, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
  • Patent number: 12014954
    Abstract: An equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. The semiconductor device includes an etch stop layer, a material layer, and a mask layer. The mask layer has openings to expose portions of the material layer. The etching device is configured to emit a plurality of directional charged particle beams to etch the exposed portions of the material layer for forming gaps in the material layer, in which the etching device has plural ion extraction apertures to emit the directional charged particle beams. A vertical distance between the semiconductor device and the ion extraction apertures is determined in accordance with a profile of each of the gap, each of the directional charged particle beams has two energy peaks at two angles, and the angles are determined in accordance with a profile of each of the gaps and the vertical distance.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chan-Syun David Yang, Li-Te Lin, Yu-Ming Lin
  • Patent number: 12009224
    Abstract: Devices and methods for selectively etching a metal nitride layer are disclosed. The methods comprise an oxidation step and an etching step which are optionally separated by a purge, and which can be repeated in a cyclical etching process.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 11, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Ren-Jie Chang, Giuseppe Alessio Verni, Qi Xie
  • Patent number: 12000062
    Abstract: A method for depositing a monocrystalline or polycrystalline tin alloy layer on an amorphous or crystallographically mis-matched substrate. The method includes selecting tin halide as the tin source; selecting an alloying metal precursor from germanium precursors, silicon precursors, and mixtures of germanium and silicon precursors; selecting a substrate from amorphous substrates and crystallographically mis-matched substrates; generating an inert gas plasma in a remote plasma generation reactor; contacting the inert gas plasma with the tin halide to provide an activated tin halide flow stream; contacting the inert gas plasma with the alloying metal precursor to provide an activated alloying metal flow stream; directing the activated tin halide flow stream and activated alloying metal flow stream to an alloy deposition chamber physically remote from the plasma chamber; and depositing the monocrystalline or polycrystalline tin alloy layer on the substrate in the deposition chamber.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 4, 2024
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Bruce B. Claflin, Gordon J. Grzybowski, Arnold M. Kiefer
  • Patent number: 11993686
    Abstract: The present application discloses a surface treatment method of a polymer for 5G, belonging to the technical field of surface treatment of polymer. By injecting and adding the oxygen elements to the polymer, the polymer matrix elements and the injected atoms can form a blend structure, which can increase the surface roughness of the polymer, improve its bonding strength with the metal, and thus enhance its anti-peel strength. The surface treatment method of the application has the surface resistivity, surface roughness, water absorption and tensile properties of the polymer all considered. The equipment used in the invention has long service life and low cost, and can realize large-scale roll-to-roll production. The method can be popularized in polymer surface treatment.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: May 28, 2024
    Assignees: Beijing Normal University, Guangdong Guangxin Ion Beam Technology Co., Ltd.
    Inventors: Bin Liao, Xiao Ouyang, Guoliang Wang, Xiaoping Ouyang, Jun Luo, Pan Pang, Lin Chen, Xu Zhang, Xianying Wu, Minju Ying
  • Patent number: 11990334
    Abstract: The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 21, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Fulford, Jodi Grzeskowiak, Anton J. Devilliers
  • Patent number: 11990348
    Abstract: A wafer processing method includes supplying a first process gas into a wafer processing apparatus, lowering a temperature of the wafer, generating plasma using the first process gas, supplying a second process gas and mixing the second process gas with the plasma, performing a plasma process on the wafer using the plasma and the second process gas, and performing an annealing process on the wafer on which the plasma process has been performed. The lowering of the temperature of the wafer includes increasing an internal pressure of the wafer processing apparatus.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: May 21, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanyeong Jeong, Hoseop Choi, Sunggil Kang, Dongkyu Shin, Sangjin An
  • Patent number: 11990346
    Abstract: A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 21, 2024
    Assignee: UNITED MICROELECTRONICS CORP
    Inventors: Chuan-Chang Wu, Zhen Wu, Hsuan-Hsu Chen, Chun-Lung Chen
  • Patent number: 11984325
    Abstract: Exemplary etching methods may include flowing an oxygen-containing precursor into a processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the processing region with the oxygen-containing precursor. The substrate may include an exposed region of a transition metal nitride and an exposed region of a metal. The contacting may form an oxidized portion of the transition metal nitride and an oxidized portion of the metal. The methods may include forming a plasma of a fluorine-containing precursor and a hydrogen-containing precursor to produce fluorine-containing plasma effluents. The methods may include removing the oxidized portion of the transition metal nitride to expose a non-oxidized portion of the transition metal nitride. The methods may include forming a plasma of a chlorine-containing precursor to produce chlorine-containing plasma effluents. The methods may include removing the non-oxidized portion of the transition metal nitride.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 14, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Baiwei Wang, Xiaolin C. Chen, Rohan Puligoru Reddy, Oliver Jan, Zhenjiang Cui, Anchuan Wang
  • Patent number: 11923193
    Abstract: There is provided a technique that includes: (a) modifying a surface of a first base exposed on a surface of substrate by supplying modifying gas to the substrate including the first base and a second base exposed on the surface of the substrate; (b) selectively forming a first film on a surface of the second base by supplying first film-forming gas to the substrate after performing (a); (c) etching the first film formed on the surface of the first base to expose the surface of the first base and remodifying the surface of the first base by supplying first fluorine-containing gas to the substrate after the first film is formed on the surface of the first base after performing (b); and (d) selectively forming a second film on the first film formed on the surface of the second base by supplying second film-forming gas to the substrate after performing (c).
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kimihiko Nakatani, Motomu Degai
  • Patent number: 11901179
    Abstract: A method for forming a layer on a substrate includes providing a substrate in a reactor of a semiconductor processing system, the reactor having a divider separating an upper chamber from a lower chamber and a substrate holder therein, the substrate having upper and lower surfaces. The wafer is positioned within the reactor using the substrate holder such that the upper surface bounds the upper chamber, a silicon-containing gas is flowed through the upper chamber to deposit a layer of the upper surface, and a halogen-containing gas is flowed through the lower chamber to etch a deposited film on at least one wall bounding the lower chamber while flowing the silicon-containing gas through the upper chamber. Semiconductor processing systems are also described.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 13, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: John Tolle, Robert Vyne
  • Patent number: 11862441
    Abstract: A plasma processing method includes providing a substrate having a recess is provided in a processing container; generating plasma in the processing container to form a film on the recess; monitoring a state of the plasma generated in the generating; and determining necessity of re-execution of the generating and processing conditions for the re-execution based on the monitored plasma state.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 2, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hironari Sasagawa, Sho Kumakura
  • Patent number: 11854770
    Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources, plasma processing apparatus, and independent temperature control of plasma processing. In at least one embodiment, a method includes introducing a process gas into a gas injection channel and generating an inductively coupled plasma within the gas injection channel. The plasma includes at least one radical species selected from oxygen, nitrogen, hydrogen, NH and helium. The method includes delivering the plasma from the plasma source to a process chamber coupled therewith by flowing the plasma through a separation grid between the plasma source and a substrate. The method includes processing the substrate. Processing the substrate includes contacting the plasma including the at least one radical species with a first side of the substrate facing the separation grid and heating the substrate using a plurality of lamps located on a second side of the substrate opposite the separation grid.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 26, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Vladimir Nagorny, Rene George
  • Patent number: 11823910
    Abstract: Methods are provided for planarizing a patterned substrate in a spatial atomic layer processing system comprising a rotating platen. The patterned substrate may generally include features having higher regions and lower regions. To planarize the patterned substrate, or reduce a height differential between the higher and lower regions, a selective atomic layer etching (ALE) process is disclosed to preferentially form a modified layer on the higher regions of the features by exposing a surface of the patterned substrate to a precursor gas while the rotating platen spins at a high rotational speed. By preferentially forming the modified layer on the higher regions of the features, and subsequently removing the modified layer, the selective ALE process described herein preferentially etches the higher regions of the features to lessen the height differential between the higher and lower regions until a desired planarization of the features is achieved.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 21, 2023
    Assignee: Tokyo Electron Limited
    Inventors: David O'Meara, Anthony Dip, Masanobu Igeta
  • Patent number: 11820918
    Abstract: A method of CMP includes providing a slurry solution including ?1 per-compound oxidizer in a concentration between 0.01 M and 2 M with a pH from 2 to 5 or 8 to 11, and ?1 buffering agent which provides a buffering ratio ?1.5 that compares an amount of a strong acid needed to reduce the pH from 9.0 to 3.0 as compared to an amount of strong acid to change the pH from 9.0 to 3.0 without the buffering agent. The slurry solution is exclusive any hard slurry particles or has only soft slurry particles that have throughout a Vickers hardness <300 Kg/mm2 or Mohs Hardness <4. The slurry solution is dispensed on a hard surface having a Vickers hardness >1,000 kg/mm2 is pressed by a polishing pad with the slurry solution in between while rotating the polishing pad relative to the hard surface.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: November 21, 2023
    Assignee: ENTEGRIS, INC.
    Inventors: Rajiv K. Singh, Arul Arjunan, Deepika Singh, Chaitanya Ginde, Puneet Jawali
  • Patent number: 11810789
    Abstract: A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 7, 2023
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Shay Reboh, Victor Boureau, Sylvain Maitrejean, Francois Andrieu
  • Patent number: 11782479
    Abstract: A method of manufacturing an electronic apparatus includes the steps of: providing an electronic panel defining a through hole; providing an electronic module having at least a portion thereof received in the through hole; providing a protective member having a first surface adjacent to the electronic panel, a hole area overlapping the through hole, a peripheral area surrounding the hole area, and a second surface facing the first surface and spaced apart from the electronic module, the providing of the protective member including: providing an unfinished protective member; attaching a film to the peripheral area; and forming a generally concave-convex pattern by contacting an acid solution with the hole area.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: October 10, 2023
    Assignee: Samsung Display Co., LTD.
    Inventors: Sang Keun Lee, Hanjong Yoo
  • Patent number: 11742203
    Abstract: The present disclosure relates to a method for growing III-V compound semiconductors on silicon-on-insulators. Starting from {111}-oriented Si seed surfaces between a buried oxide layer and a patterned mask layer, the III-V compound semiconductor is grown within lateral trenches by metal organic chemical vapor deposition such that the non-defective portion of the III-V compound semiconductor formed on the buried oxide layer is substantially free of crystalline defects and has high crystalline quality.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 29, 2023
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Kei May Lau, Yu Han
  • Patent number: 11732366
    Abstract: A method for chemical processing an internal cavity of an additive manufactured (AM) metal workpiece is disclosed in which a connector is provided in fluid connection with the internal cavity and a chemical polishing solution is flowed through the connector and the internal cavity to process the internal cavity to a desired finish.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: August 22, 2023
    Assignee: REM TECHNOLOGIES, INC.
    Inventors: Agustin Diaz, Gary J. Sroka
  • Patent number: 11728176
    Abstract: A treatment method is provided that includes an embedding step of embedding an organic film in an undercoat film in which a depression is formed; and an etching step of performing etching, after the embedding step, until at least a portion of a top of the undercoat film is exposed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 15, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Kiyohito Ito, Shinya Morikita, Kensuke Taniguchi, Michiko Nakaya, Masanobu Honda