Patents Examined by Thomas T Pham
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Patent number: 11923193Abstract: There is provided a technique that includes: (a) modifying a surface of a first base exposed on a surface of substrate by supplying modifying gas to the substrate including the first base and a second base exposed on the surface of the substrate; (b) selectively forming a first film on a surface of the second base by supplying first film-forming gas to the substrate after performing (a); (c) etching the first film formed on the surface of the first base to expose the surface of the first base and remodifying the surface of the first base by supplying first fluorine-containing gas to the substrate after the first film is formed on the surface of the first base after performing (b); and (d) selectively forming a second film on the first film formed on the surface of the second base by supplying second film-forming gas to the substrate after performing (c).Type: GrantFiled: February 25, 2021Date of Patent: March 5, 2024Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Kimihiko Nakatani, Motomu Degai
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Patent number: 11901179Abstract: A method for forming a layer on a substrate includes providing a substrate in a reactor of a semiconductor processing system, the reactor having a divider separating an upper chamber from a lower chamber and a substrate holder therein, the substrate having upper and lower surfaces. The wafer is positioned within the reactor using the substrate holder such that the upper surface bounds the upper chamber, a silicon-containing gas is flowed through the upper chamber to deposit a layer of the upper surface, and a halogen-containing gas is flowed through the lower chamber to etch a deposited film on at least one wall bounding the lower chamber while flowing the silicon-containing gas through the upper chamber. Semiconductor processing systems are also described.Type: GrantFiled: October 25, 2021Date of Patent: February 13, 2024Assignee: ASM IP Holding B.V.Inventors: John Tolle, Robert Vyne
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Patent number: 11862441Abstract: A plasma processing method includes providing a substrate having a recess is provided in a processing container; generating plasma in the processing container to form a film on the recess; monitoring a state of the plasma generated in the generating; and determining necessity of re-execution of the generating and processing conditions for the re-execution based on the monitored plasma state.Type: GrantFiled: May 26, 2021Date of Patent: January 2, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Hironari Sasagawa, Sho Kumakura
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Patent number: 11854770Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources, plasma processing apparatus, and independent temperature control of plasma processing. In at least one embodiment, a method includes introducing a process gas into a gas injection channel and generating an inductively coupled plasma within the gas injection channel. The plasma includes at least one radical species selected from oxygen, nitrogen, hydrogen, NH and helium. The method includes delivering the plasma from the plasma source to a process chamber coupled therewith by flowing the plasma through a separation grid between the plasma source and a substrate. The method includes processing the substrate. Processing the substrate includes contacting the plasma including the at least one radical species with a first side of the substrate facing the separation grid and heating the substrate using a plurality of lamps located on a second side of the substrate opposite the separation grid.Type: GrantFiled: January 14, 2021Date of Patent: December 26, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Wei Liu, Vladimir Nagorny, Rene George
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Patent number: 11820918Abstract: A method of CMP includes providing a slurry solution including ?1 per-compound oxidizer in a concentration between 0.01 M and 2 M with a pH from 2 to 5 or 8 to 11, and ?1 buffering agent which provides a buffering ratio ?1.5 that compares an amount of a strong acid needed to reduce the pH from 9.0 to 3.0 as compared to an amount of strong acid to change the pH from 9.0 to 3.0 without the buffering agent. The slurry solution is exclusive any hard slurry particles or has only soft slurry particles that have throughout a Vickers hardness <300 Kg/mm2 or Mohs Hardness <4. The slurry solution is dispensed on a hard surface having a Vickers hardness >1,000 kg/mm2 is pressed by a polishing pad with the slurry solution in between while rotating the polishing pad relative to the hard surface.Type: GrantFiled: July 1, 2021Date of Patent: November 21, 2023Assignee: ENTEGRIS, INC.Inventors: Rajiv K. Singh, Arul Arjunan, Deepika Singh, Chaitanya Ginde, Puneet Jawali
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Patent number: 11823910Abstract: Methods are provided for planarizing a patterned substrate in a spatial atomic layer processing system comprising a rotating platen. The patterned substrate may generally include features having higher regions and lower regions. To planarize the patterned substrate, or reduce a height differential between the higher and lower regions, a selective atomic layer etching (ALE) process is disclosed to preferentially form a modified layer on the higher regions of the features by exposing a surface of the patterned substrate to a precursor gas while the rotating platen spins at a high rotational speed. By preferentially forming the modified layer on the higher regions of the features, and subsequently removing the modified layer, the selective ALE process described herein preferentially etches the higher regions of the features to lessen the height differential between the higher and lower regions until a desired planarization of the features is achieved.Type: GrantFiled: July 31, 2020Date of Patent: November 21, 2023Assignee: Tokyo Electron LimitedInventors: David O'Meara, Anthony Dip, Masanobu Igeta
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Patent number: 11810789Abstract: A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.Type: GrantFiled: December 11, 2019Date of Patent: November 7, 2023Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Shay Reboh, Victor Boureau, Sylvain Maitrejean, Francois Andrieu
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Patent number: 11782479Abstract: A method of manufacturing an electronic apparatus includes the steps of: providing an electronic panel defining a through hole; providing an electronic module having at least a portion thereof received in the through hole; providing a protective member having a first surface adjacent to the electronic panel, a hole area overlapping the through hole, a peripheral area surrounding the hole area, and a second surface facing the first surface and spaced apart from the electronic module, the providing of the protective member including: providing an unfinished protective member; attaching a film to the peripheral area; and forming a generally concave-convex pattern by contacting an acid solution with the hole area.Type: GrantFiled: November 5, 2020Date of Patent: October 10, 2023Assignee: Samsung Display Co., LTD.Inventors: Sang Keun Lee, Hanjong Yoo
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Patent number: 11742203Abstract: The present disclosure relates to a method for growing III-V compound semiconductors on silicon-on-insulators. Starting from {111}-oriented Si seed surfaces between a buried oxide layer and a patterned mask layer, the III-V compound semiconductor is grown within lateral trenches by metal organic chemical vapor deposition such that the non-defective portion of the III-V compound semiconductor formed on the buried oxide layer is substantially free of crystalline defects and has high crystalline quality.Type: GrantFiled: February 26, 2020Date of Patent: August 29, 2023Assignee: The Hong Kong University of Science and TechnologyInventors: Kei May Lau, Yu Han
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Patent number: 11732366Abstract: A method for chemical processing an internal cavity of an additive manufactured (AM) metal workpiece is disclosed in which a connector is provided in fluid connection with the internal cavity and a chemical polishing solution is flowed through the connector and the internal cavity to process the internal cavity to a desired finish.Type: GrantFiled: February 15, 2017Date of Patent: August 22, 2023Assignee: REM TECHNOLOGIES, INC.Inventors: Agustin Diaz, Gary J. Sroka
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Patent number: 11728176Abstract: A treatment method is provided that includes an embedding step of embedding an organic film in an undercoat film in which a depression is formed; and an etching step of performing etching, after the embedding step, until at least a portion of a top of the undercoat film is exposed.Type: GrantFiled: August 8, 2019Date of Patent: August 15, 2023Assignee: Tokyo Electron LimitedInventors: Kiyohito Ito, Shinya Morikita, Kensuke Taniguchi, Michiko Nakaya, Masanobu Honda
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Patent number: 11710633Abstract: A method of depositing a silicon film on a recess formed in a surface of a substrate is provided. The substrate is placed on a rotary table in a vacuum vessel, so as to pass through first, second, and third processing regions in the vacuum vessel. An interior of the vacuum vessel is set to a first temperature capable of breaking an Si—H bond. In the first processing region, Si2H6 gas having a temperature less than the first temperature is supplied to form an SiH3 molecular layer on its surface. In the second processing region, a silicon atomic layer is exposed on the surface of the substrate, by breaking the Si—H bond in the SiH3 molecular layer. In the third processing region, by anisotropic etching, the silicon atomic layer on an upper portion of an inner wall of the recess is selectively removed.Type: GrantFiled: January 22, 2021Date of Patent: July 25, 2023Assignee: Tokyo Electron LimitedInventor: Hitoshi Kato
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Patent number: 11702569Abstract: A slurry containing abrasive grains, a liquid medium, and a salt of a compound represented by formula (1) below, in which the abrasive grains include first particles and second particles in contact with the first particles, the first particles contain cerium oxide, and the second particles contain a hydroxide of a tetravalent metal element. [In formula (1), R represents a hydroxyl group or a monovalent organic group].Type: GrantFiled: August 30, 2018Date of Patent: July 18, 2023Assignee: RESONAC CORPORATIONInventors: Takaaki Matsumoto, Tomohiro Iwano, Tomoyasu Hasegawa
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Patent number: 11697766Abstract: A method 14 for the controlled removal of a protective layer 3 from a surface of a component 10, wherein the component comprises: a base body 1; an intermediate layer 2, which at least partially covers the base body; and said protective layer 3, which comprises an amorphous solid, in particular an amorphous nonmetal, in particular amorphous ceramic, and at least partially covers the intermediate layer; wherein the method comprises the following steps: bringing 11 the protective layer 3 into contact with an etching or solvent medium 4; and removing 12 the protective layer 3 under the action of the etching or solvent medium 4 until the intermediate layer 2 is exposed; and wherein the etching or solvent medium causes a first etching or dissolving speed of the protective layer and a second etching or dissolving speed of the intermediate layer and wherein the first etching or dissolving speed is greater than the second etching or dissolving speed.Type: GrantFiled: May 14, 2018Date of Patent: July 11, 2023Assignee: Inficon Holding AGInventors: Bernhard Andreaus, Claudio Christoffel, Philip Spring
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Patent number: 11688650Abstract: A method of etching a substrate, on which a multilayered film is formed, is provided. The multilayered film includes a silicon-containing insulating layer, an undercoat layer provided under the silicon-containing insulating layer, and a mask layer provided above the silicon-containing insulating layer. When the substrate is loaded into a process chamber, a process gas containing a fluorocarbon gas and a noble gas is supplied into the process chamber, and the multilayered film is etched by the plasma formed from the process gas. The noble gas contains a first gas having higher ionization energy than Ar gas, and momentum of an ionized particle of the first gas is less than momentum of an ionized particle of Ar gas.Type: GrantFiled: July 1, 2020Date of Patent: June 27, 2023Assignee: Tokyo Electron LimitedInventors: Gaku Shimoda, Masayuki Sawataishi, Takanori Eto
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Patent number: 11682560Abstract: Exemplary etching methods may include flowing a halogen-containing precursor into a substrate processing region of a semiconductor processing chamber. The halogen-containing precursor may be characterized by a gas density greater than or about 5 g/L. The methods may include contacting a substrate housed in the substrate processing region with the halogen-containing precursor. The substrate may define an exposed region of a hafnium-containing material. The methods may also include removing the hafnium-containing material.Type: GrantFiled: October 11, 2018Date of Patent: June 20, 2023Assignee: Applied Materials, Inc.Inventors: Zhenjiang Cui, Hanshen Zhang, Daniella Holm
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Patent number: 11682554Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a boron-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the boron-containing precursor at a temperature above about 250° C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.Type: GrantFiled: April 20, 2021Date of Patent: June 20, 2023Assignee: Applied Materials, Inc.Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick
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Patent number: 11676812Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.Type: GrantFiled: June 17, 2020Date of Patent: June 13, 2023Assignee: ASM IP Holding B.V.Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
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Patent number: 11661332Abstract: Methods and systems for reducing stiction through roughening the surface and reducing the contact area in MEMS devices are disclosed. A method includes fabricating bumpstops on a surface of a MEMS device substrate to reduce stiction. Another method is directed to applying roughening etchant to a surface of a silicon substrate to enhance roughness after cavity etch and before removal of hardmask. Another embodiment described herein is directed to a method to reduce contact area between proof mass and UCAV (“upper cavity”) substrate surface with minimal impact on the cavity volume by introducing a shallow etch process step and maintaining high pressure in accelerometer cavity. Another method is described as to increasing the surface roughness of a UCAV substrate surface by depositing a rough layer (e.g. polysilicon) on the surface of the substrate and etching back the rough layer to transfer the roughness.Type: GrantFiled: February 19, 2020Date of Patent: May 30, 2023Assignee: InvenSense, Inc.Inventors: Daesung Lee, Ian Flader, Alan Cuthbertson, Emad Mehdizadeh
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Patent number: 11651977Abstract: Methods for processing a workpiece are provided. Conducting a thermal treatment on a workpiece are provided. The workpiece contains at least one layer of metal. The method can include generating one or more species from a process gas. The process gas can include hydrogen or deuterium. The method can include filtering the one or more species to create a filtered mixture and exposing the workpiece to the filtered mixture. An oxidation process on a workpiece are provided. The method can be conducted at a process temperature of less than 350° C.Type: GrantFiled: March 30, 2021Date of Patent: May 16, 2023Assignees: BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY CO., LTD, MATTSON TECHNOLOGY, INC.Inventors: Shanyu Wang, Chun Yan