Patents Examined by Thomas T Pham
  • Patent number: 11018014
    Abstract: A dry etching method for isotropically etching each of SiGe layers selectively relative to each of Si layers in a laminated film is provided. The laminated film can include Si layers and SiGe layers alternately and repeatedly laminated. Each of the SiGe layers can be plasma-etched with plasma generated by a pulse-modulated radio frequency power using NF3 gas.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 25, 2021
    Inventors: Ze Shen, Tetsuo Ono, Hisao Yasunami
  • Patent number: 11011351
    Abstract: Systems and methods for generating monoenergetic ions are described. A duty cycle of a high parameter level of a multistate parameter signal is maintained and a difference between the high parameter level and a low parameter level of the multistate parameter signal is maintained to generate monoenergetic ions. The monoenergetic ions are used to etch a top material layer of a substrate at a rate that is self-limiting without substantially etching a bottom material layer of the substrate.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 18, 2021
    Assignee: Lam Research Corporation
    Inventors: Juline Shoeb, Alexander Miller Paterson, Ying Wu
  • Patent number: 10995269
    Abstract: An etchant composition includes an inorganic acid, a siloxane compound, an ammonium compound, and a solvent, wherein the siloxane compound is represented by General Formula (I): A method of fabricating an integrated circuit device includes forming a structure on a substrate, the structure having a surface on which an oxide film and a nitride film are exposed; and selectively removing the nitride film from the oxide film and the nitride film by bringing the etchant composition into contact with the structure.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 4, 2021
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Jin-Woo Lee, Hoon Han, Keon-Young Kim, Jung-Hun Lim, Jin-Uk Lee, Jae-Wan Park
  • Patent number: 10991572
    Abstract: The present disclosure discloses a manufacturing method for a semiconductor apparatus, and relates to the field of semiconductor technologies. Forms of the method include: providing a semiconductor structure, where the semiconductor structure includes: a substrate and an interlayer dielectric layer on the substrate, where the interlayer dielectric layer has an opening for forming a gate; depositing a gate metal layer on the semiconductor structure to fill the opening, where the gate metal layer contains impurity; forming an impurity adsorption layer on the gate metal layer; performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer; and removing the impurity adsorption layer after the first annealing treatment is performed.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Jin E Liang, Le Lv
  • Patent number: 10991623
    Abstract: A wafer processing method for processing a wafer having a substrate and a device layer formed on a front side of the substrate includes forming a mask on a back side of the wafer, so as to form an etched groove along each street through a thickness of the substrate from the back side of the wafer, performing plasma etching from the back side of the wafer through the mask to the substrate after forming the mask, thereby forming the etched groove in the substrate along each street so that the etched groove has a depth equal to the thickness of the substrate, and applying a laser beam to the device layer along each street from the front side of the wafer before etching and mask forming, thereby forming a device layer dividing groove corresponding to the etched groove along each street.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 27, 2021
    Inventors: Masatoshi Wakahara, Karl Heinz Priewasser, Meiya Piao, Kentaro Odanaka, Wakana Onoe, Heidi Lan
  • Patent number: 10964540
    Abstract: The present disclosure provides a semiconductor structure forming method, including: providing a base, a first mask layer and a second mask layer located at the top of the first mask layer being formed on the base, and the second mask layer internally having a first opening, a second opening and a third opening; forming first side wall layers on a side wall of the first opening, a side wall of the second opening and a side wall of the third opening; forming a first pattern layer filling the first opening, the second opening and the third opening, the first pattern layer internally having a first groove; etching to remove the second mask layer located between the second opening and the third opening along the bottom of the first groove, so as to form fourth openings located between adjacent first side wall layers; and by using the second mask layer and the first side wall layers as masks, etching the first mask layer below the first opening, the second opening, the third opening and the fourth openings, so as
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Xiao Fangyuan
  • Patent number: 10966333
    Abstract: This application provides a method of manufacturing a case, a case and an electronic device. This method may include providing a metal case with a surface; applying a first oxidation treatment on the surface of the metal case to form a first oxidation layer; defining a first area on the surface; removing a portion of the first oxidation layer located within the first area; applying a second oxidation treatment on the surface within the first area to form a second oxidation layer, and forming a paint layer on the second oxidation layer by spraying.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 30, 2021
    Inventors: Mingren Chen, Tibo Hou
  • Patent number: 10950452
    Abstract: A time required to return an inside of the chamber after performing maintenance of the inside of the chamber into a state prior to the maintenance can be shortened. A seasoning method includes a first dry cleaning process of cleaning the inside of the chamber by supplying an O2 gas into the chamber and generating plasma of the O2 gas within the chamber; and a second dry cleaning process of seasoning, after the first dry cleaning process, the inside of the chamber by supplying a processing gas containing fluorine into the chamber and generating plasma of the processing gas within the chamber.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 16, 2021
    Inventors: Yoshio Ishikawa, Takashi Enomoto, Yutaka Osada
  • Patent number: 10923358
    Abstract: In a substrate processing method for etching a silicon oxide layer formed on a surface of a substrate, a surface of the silicon oxide layer is hydrophilized. Then, the silicon oxide layer is etched by supplying a halogen-containing gas to the substrate and sublimating a reaction product generated by reaction between the halogen-containing gas and the silicon oxide layer.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: February 16, 2021
    Inventors: Muneyuki Imai, Akitaka Shimizu
  • Patent number: 10818502
    Abstract: Systems and methods are disclosed for plasma discharge ignition to reduce surface particles and thereby decrease defects introduced during plasma processing. A microelectronic workpiece is positioned on a holder within a process chamber that includes a first radio frequency (RF) power source configured to couple RF power to a top portion of the process chamber, a second RF power source configured to couple RF power to the holder, and a direct current (DC) power supply. Initially, a process gas for plasma process is flowed into the process chamber. The process gas is ignited to form plasma by activating the second RF power source to apply RF power to the holder. Subsequently, the microelectronic workpiece is clamped to the holder by applying the positive voltage to the holder with the DC power supply, and the first RF power source is activated to maintain the plasma within the process chamber.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 27, 2020
    Inventors: Sergey Voronin, Jason Marion, Yusuke Yoshida, Alok Ranjan, Takashi Enomoto, Yoshio Ishikawa
  • Patent number: 10796914
    Abstract: In various embodiments, a method for processing a wafer is provided. The method includes forming a layer stack, including a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, a lower mechanical and/or chemical resistance than the support layer and than the useful layer. The support layer has a depression, which exposes the sacrificial region. The method further includes forming at least one channel in the exposed sacrificial region by means of the processing fluid. The channel connects the depression to an exterior of the layer stack.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 6, 2020
    Assignee: Infineon Technologies AG
    Inventor: Francisco Javier Santos Rodriguez
  • Patent number: 10793468
    Abstract: A method of manufacturing an etched glass article includes the steps of jetting an image with a UV curable inkjet ink on a surface of the glass article; UV curing the image; etching the surface not covered by the UV cured image to obtain an etched image; and removing the UV cured image in an aqueous alkaline solution; wherein the UV curable inkjet ink includes a polymerizable composition, wherein at least 80 wt % of the polymerizable composition consists of: a) 15.0 to 70.0 wt % of an acryl amide; b) 20.0 to 75.0 wt % of a polyfunctional acrylate; and c) 1.0 to 15.0 wt % of a (meth)acrylate containing a carboxylic acid group, a phosphoric acid group or a phosphonic acid group-; with all weight percentages (wt %) based on the total weight of the polymerizable composition.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 6, 2020
    Inventors: Rita Torfs, Frank Louwet, Johan Loccufier, Mark Lens
  • Patent number: 10784107
    Abstract: Methods of forming self-aligned patterns are described. A film material is deposited on a patterned film to fill and cover features formed by the patterned film. The film material is recessed to a level below the top of the patterned film. The recessed film is converted to a metal film by exposure to a metal precursor followed by volumetric expansion of the metal film.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: September 22, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Pramit Manna, Yihong Chen, Ziqing Duan, Rui Cheng, Shishi Jiang
  • Patent number: 10784119
    Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 22, 2020
    Inventors: Ravi Prakash Srivastava, Hsueh-Chung Chen, Steven McDermott, Martin O'Toole, Brendan O'Brien, Terry A. Spooner
  • Patent number: 10770286
    Abstract: A method for selectively forming a silicon nitride film on a substrate comprising a first metallic surface and a second dielectric surface by a cyclical deposition process is disclosed. The method may comprise contacting the substrate with a first reactant comprising a silicon halide source and contacting the substrate with a second reactant comprising a nitrogen source, wherein the incubation period for the first metallic surface is less than the incubation period for the second dielectric surface. Semiconductor device structures comprising a selective silicon nitride film are also disclosed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: September 8, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Jacob Huffman Woodruff, Bed Sharma
  • Patent number: 10745588
    Abstract: This invention provides a silicon wafer polishing composition used in the presence of an abrasive. The composition comprises a silicon wafer polishing accelerator, an amide group-containing polymer, and water. The amide group-containing polymer has a building unit A in its main chain. The building unit A comprises a main chain carbon atom constituting the main chain of the amide group-containing polymer and a secondary amide group or a tertiary amide group. The carbonyl carbon atom constituting the secondary amide group or tertiary amide group is directly coupled to the main chain carbon atom.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 18, 2020
    Inventors: Kohsuke Tsuchiya, Hisanori Tansho, Taiki Ichitsubo, Yoshio Mori
  • Patent number: 10727075
    Abstract: Embodiments of the present disclosure generally provide a method and apparatus for forming features in a material layer utilizing EUV technologies. In one embodiment, a method of patterning a substrate includes disposing a patterned photoresist layer on a mask layer disposed on a substrate, wherein the patterned photoresist layer has openings with different widths defined in the patterned photoresist layer, forming a compensatory layer along sidewalls of the patterned photoresist layer to modify the widths of the openings and etching the mask layer through the openings with the modified width.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 28, 2020
    Inventors: Sang Wook Kim, Zhibin Wang, Kyoungjin Lee, Byungkook Kong
  • Patent number: 10729018
    Abstract: To stably produce a laminate wherein heat resistant resin layers are laminated on both surfaces of a fluorinated resin layer, by thermal lamination.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 28, 2020
    Assignee: AGC Inc.
    Inventors: Toru Sasaki, Wataru Kasai
  • Patent number: 10720322
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Patent number: 10685871
    Abstract: The present invention provides a method for fabricating a semiconductor structure. A multilayer structure on is formed a substrate, the multilayer structure includes at least a first dielectric layer, a second dielectric layer and an amorphous silicon layer, next, a first etching step is performed, to forma first recess in the amorphous silicon layer and in the second dielectric layer, parts of the first dielectric layer is exposed by the first recess, afterwards, a hard mask layer is formed in the first recess, a second etching step is then performed to remove the hard mask layer and to expose a surface of the first dielectric layer, and a third etching step is performed with the remaining hard mask layer, to remove a portion of the first dielectric layer, so as to form a second recess in the first dielectric layer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee