Patents Examined by Thomas T Pham
  • Patent number: 11171011
    Abstract: A method of forming a feature in a stack comprising a dielectric material on a substrate is provided. An etch plasma is generated from an etch gas, exposing the stack to the etch plasma and partially etching the feature in the stack. The stack is primed. A protective film is deposited on sidewalls of the feature by repeating for a plurality of cycles the steps of exposing the stack to a first reactant, allowing the first reactant to adsorb onto the stack, and exposing the stack to a second reactant, wherein the first and second reactants react with one another to form the protective film over the stack. The etching, priming, and depositing a protective film are repeated until the feature is etched to a final depth.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 9, 2021
    Assignee: Lam Research Corporation
    Inventors: Eric Hudson, Kalman Pelhos
  • Patent number: 11171010
    Abstract: Embodiments described herein relate to methods forming optical device structures. One embodiment of the method includes exposing a substrate to ions at an ion angle relative to a surface normal of a surface of the substrate to form an initial depth of a plurality of depths. A patterned mask is disposed over the substrate and includes two or more projections defining exposed portions of the substrate or a device layer disposed on the substrate. Each projection has a trailing edge at a bottom surface contacting the device layer, a leading edge at a top surface of each projection, and a height from the top surface to the device layer. Exposing the substrate to ions at the ion angle is repeated to form at least one subsequent depth of the plurality of depths.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ludovic Godet, Rutger Meyer Timmerman Thijssen
  • Patent number: 11164753
    Abstract: Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: November 2, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ning Li, Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Keiichi Tanaka, Steven D. Marcus
  • Patent number: 11158515
    Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Rahim Kasim, Manish Chandhok, Florian Gstrein
  • Patent number: 11158517
    Abstract: A method for selective plasma etching of silicon oxide relative to silicon nitride. The method includes a) providing a substrate containing a silicon oxide film and a silicon nitride film, b) exposing the substrate to a plasma-excited treatment gas containing 1) H2 and 2) HF, F2, or both HF and F2, to form a silicon oxide surface layer with reduced oxygen content on the silicon oxide film and form an ammonium salt layer on the silicon nitride film, c) exposing the substrate to a plasma-excited halogen-containing gas that reacts with and removes the silicon oxide surface layer from the silicon oxide film, and d) repeating steps b) and c) at least once to further selectively etch the silicon oxide film relative to the ammonium salt layer on the silicon nitride film. The ammonium salt layer may be removed when the desired etching has been achieved.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 26, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Du Zhang, Yu-Hao Tsai, Mingmei Wang
  • Patent number: 11152220
    Abstract: The present disclosure relates to the field of semiconductor device etching process, and specifically discloses an etching method and a semiconductor device. The etching method comprises: providing a substrate on which a film layer to be etched is formed; forming a mask layer structure on the film layer to be etched, wherein the mask layer structure includes a dielectric layer formed on an upper surface of the film layer to be etched and an APF layer formed on an upper surface of the dielectric layer; patterning the APF layer; performing a first etching process on the dielectric layer and the film layer to be etched by using the patterned APF layer as a mask to pattern the dielectric layer and partially etch the film layer to be etched; removing the patterned APF layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 19, 2021
    Assignee: Shanghai Huali Integrated Circuit Mfg. Co. Ltd.
    Inventors: Penggang Han, Pengkai Xu
  • Patent number: 11136504
    Abstract: An etchant composition for wet etching a titanium-containing film. The etchant composition includes hydrofluoric acid as a primary oxidant, a co-oxidant that forms a dense oxide film on a surface of a titanium film during an etching process, an alkali metal salt that inhibits aggregation and adsorption of titanium ions during the etching process, and a solvent.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: October 5, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Qilin Hao
  • Patent number: 11127593
    Abstract: A method of patterning a substrate may include providing a cavity in a layer, disposed on the substrate. The cavity may have a first length along a first direction and a first width along a second direction, perpendicular to the first direction. The method may include directing first angled ions in a first exposure to the cavity, wherein after the first exposure the cavity has a second length, greater than the first length; directing normal ions in a second exposure to the cavity, wherein the cavity retains the second length after the second exposure; and directing second angled ions to the cavity is a third exposure, subsequent to the second exposure, wherein the cavity has a third length, greater than the second length, after the third exposure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 21, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin R. Anglin, Simon Ruffell
  • Patent number: 11107695
    Abstract: Apparatus, systems, and methods for processing workpieces are provided. In one example implementation, a fluorine and oxygen plasma-based process can be used to smooth a roughened surface of a silicon and/or a silicon containing structure. The process can include generating species from a process gas using an inductive coupling element in a first chamber. The process can include introducing a fluorine containing gas and an oxygen containing gas with the species to create a mixture. The process can further include exposing the silicon and/or the silicon containing structure to the mixture such that the mixture at least partially etches a roughened portion to leave a smoother surface of the silicon and/or the silicon containing structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 31, 2021
    Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.
    Inventors: Qi Zhang, Xinliang Lu, Hua Chung
  • Patent number: 11101140
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Patent number: 11078380
    Abstract: A method of CMP includes providing a slurry solution including ?1 per-compound oxidizer in a concentration between 0.01 M and 2 M with a pH from 2 to 5 or 8 to 11, and ?1 buffering agent which provides a buffering ratio ?1.5 that compares an amount of a strong acid needed to reduce the pH from 9.0 to 3.0 as compared to an amount of strong acid to change the pH from 9.0 to 3.0 without the buffering agent. The slurry solution is exclusive any hard slurry particles or has only soft slurry particles that have throughout a Vickers hardness <300 Kg/mm2 or Mohs Hardness <4. The slurry solution is dispensed on a hard surface having a Vickers hardness >1,000 kg/mm2 is pressed by a polishing pad with the slurry solution in between while rotating the polishing pad relative to the hard surface.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 3, 2021
    Assignees: Entegris, Inc., University of Florida Research Foundation, Inc.
    Inventors: Rajiv K. Singh, Arul Arjunan, Deepika Singh, Chaitanya Ginde, Puneet N. Jawali
  • Patent number: 11061324
    Abstract: A method of manufacturing a replica template includes preparing a substrate including a first protruding portion protruding from a first surface of the substrate and having a patterning surface thereon, forming a first mask pattern over the patterning surface, the first mask pattern comprising a convex portion having a smaller width than the patterning surface and a pattern disposed on the convex portion, removing a portion of the first protruding portion using the first mask pattern as a mask to produce a second protruding portion on the first protruding portion, and forming a pattern in the patterning surface on the second protruding portion by transferring the shape of the pattern of the first mask pattern into the patterning surface on the second protruding portion.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mana Tanabe, Shingo Kanamitsu
  • Patent number: 11056320
    Abstract: An apparatus comprises a housing having a process space, a support unit supporting the substrate in the process space, a process gas supply unit supplying a process gas into the process space, and a plasma source generating plasma from the process gas. The support unit comprises a support member on which the substrate is placed, a heating member that heats the substrate supported on the support member, and a heat transfer gas supply member that supplies a heat transfer gas to a backside of the substrate. The heating member comprises heaters that heat regions on the substrate on the support member viewed from above. The support member comprises a protrusion that partitions a space between the support member and the backside of the substrate placed on the support member into gas regions, and at least one of heating regions is divided into regions by the protrusion viewed from above.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 6, 2021
    Assignee: SEMES CO., LTD.
    Inventors: Sang-Kee Lee, Kang Rae Ha
  • Patent number: 11053595
    Abstract: Compositions and methods for etching cobalt chromium alloys are disclosed. The compositions generally include at least two mineral acids, certain component metals of the alloy to be etched, and optionally iron (Fe). For example, when etching a cobalt chromium molybdenum alloy, the metals may include chromium (Cr), molybdenum (Mo), and optionally, cobalt (Co). The at least two mineral acids may include hydrochloric acid (HCl), nitric acid (HNO3), and hydrofluoric acid (HF). The methods provide for etching an entire surface of a substrate or etching a surface of a substrate in a pattern using selective coating patterns and/or coating removal. Thus, unlimited patterns, as well as etch depths and variations in etch depths are achievable using the compositions and methods disclosed.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 6, 2021
    Assignee: Tech Met, Inc.
    Inventors: Michael Vidra, Daniel Jon Schutzer
  • Patent number: 11041097
    Abstract: A polishing composition and a method of fabricating a semiconductor device using the same, the polishing composition including an abrasive; a first additive that includes a C5 to C30 hydrocarbon including an amide group and a carboxyl group or a C5 to C30 hydrocarbon including two or more amine groups; and a second additive that includes a sulfonic acid, a sulfonate, or a sulfonate salt.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: June 22, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Soulbrain Co., Ltd.
    Inventors: Kyung-il Park, Myeong Hoon Han, Sanghyun Park, Wonki Hur, Seungho Park, Hao Cui
  • Patent number: 11043391
    Abstract: A method of etching silicon-containing film formed on an electrode layer of a floating potential is provided. The etching is performed in a processing vessel while supplying gas, a first high frequency electric power of a first frequency, and a second high frequency electric power of a second frequency less than the first frequency. The method includes a step of supplying, during etching of the silicon-containing film, the first high frequency electric power as a continuous wave and the second high frequency electric power as a pulse wave having a duty cycle of 20% or less, upon a distance from the electrode layer to a bottom of an etching pattern formed on the silicon-containing film becoming not more than a predetermined distance.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 22, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Yusuke Saitoh
  • Patent number: 11018014
    Abstract: A dry etching method for isotropically etching each of SiGe layers selectively relative to each of Si layers in a laminated film is provided. The laminated film can include Si layers and SiGe layers alternately and repeatedly laminated. Each of the SiGe layers can be plasma-etched with plasma generated by a pulse-modulated radio frequency power using NF3 gas.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 25, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Ze Shen, Tetsuo Ono, Hisao Yasunami
  • Patent number: 11011351
    Abstract: Systems and methods for generating monoenergetic ions are described. A duty cycle of a high parameter level of a multistate parameter signal is maintained and a difference between the high parameter level and a low parameter level of the multistate parameter signal is maintained to generate monoenergetic ions. The monoenergetic ions are used to etch a top material layer of a substrate at a rate that is self-limiting without substantially etching a bottom material layer of the substrate.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 18, 2021
    Assignee: Lam Research Corporation
    Inventors: Juline Shoeb, Alexander Miller Paterson, Ying Wu
  • Patent number: 10995269
    Abstract: An etchant composition includes an inorganic acid, a siloxane compound, an ammonium compound, and a solvent, wherein the siloxane compound is represented by General Formula (I): A method of fabricating an integrated circuit device includes forming a structure on a substrate, the structure having a surface on which an oxide film and a nitride film are exposed; and selectively removing the nitride film from the oxide film and the nitride film by bringing the etchant composition into contact with the structure.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 4, 2021
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Jin-Woo Lee, Hoon Han, Keon-Young Kim, Jung-Hun Lim, Jin-Uk Lee, Jae-Wan Park
  • Patent number: 10991623
    Abstract: A wafer processing method for processing a wafer having a substrate and a device layer formed on a front side of the substrate includes forming a mask on a back side of the wafer, so as to form an etched groove along each street through a thickness of the substrate from the back side of the wafer, performing plasma etching from the back side of the wafer through the mask to the substrate after forming the mask, thereby forming the etched groove in the substrate along each street so that the etched groove has a depth equal to the thickness of the substrate, and applying a laser beam to the device layer along each street from the front side of the wafer before etching and mask forming, thereby forming a device layer dividing groove corresponding to the etched groove along each street.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 27, 2021
    Assignee: DISCO CORPORATION
    Inventors: Masatoshi Wakahara, Karl Heinz Priewasser, Meiya Piao, Kentaro Odanaka, Wakana Onoe, Heidi Lan