Patents Examined by Thong Le
  • Patent number: 7057949
    Abstract: Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: June 6, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Feng Pan, Weng Fook Lee, Edward V. Bautista, Jr., Santosh K. Yachareni
  • Patent number: 7050349
    Abstract: A programming circuit includes an LT fuse read circuit programming a defective address during a wafer-processing, an electrical fuse circuit electrically programming a defective address, an electrical fuse circuit storing therein whether the electrical fuse circuit is used, a select circuit receiving data programmed by the LT fuse and that programmed by the electrical fuse for switch and output, an electrical fuse circuit designating a switching of the select circuit, and a repair decision circuit comparing an output received from the select circuit and an input address received from the address buffer.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: May 23, 2006
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventor: Hiroaki Tanizaki
  • Patent number: 6987690
    Abstract: A program unit includes two program cells having an electric resistance varying according to a magnetization direction thereof. These program cells are magnetized in the same direction in initial state, that is, non-program state. In program state, the magnetization direction of one of the program cells selected according to program data is changed from the initial state. One-bit program data and information of whether the program unit stores program data or not can be read based on two program signals generated according to the electric resistances of the two program cells.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: January 17, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Patent number: 6906963
    Abstract: Provided is a semiconductor memory device having an output driver for high frequency operation. In the output driver of the semiconductor memory device, a first NMOS transistor and a second NMOS transistor are connected in series, the drain of the first NMOS transistor is connected to an output pad, and the source of the second NMOS transistor is connected to a ground voltage. In addition, a first internal voltage is applied to the gate of the first NMOS transistor, a second internal voltage is applied to a gate of the second NMOS transistor, and a voltage level of the second internal voltage is lower than the voltage level of an external supply voltage. The second internal voltage is generated directly from an internal voltage generating circuit of the semiconductor memory device or is externally applied. The voltage level of the second internal voltage is different from the level of an operating voltage of the semiconductor memory device.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: June 14, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sung Song, Ki-whan Song, Dong-su Lee
  • Patent number: 6859409
    Abstract: The semiconductor memory device includes a plurality of first data sense amplifiers and a plurality of second data sense amplifiers. Each first data sense amplifier being a voltage sense amplifier, and each first data sense amplifier associated with data lines of a first type, which lead from bit line sense amplifiers. Each second data sense amplifier including a current sense amplifier and a voltage sense amplifier, and each second data sense amplifier associated with data lines of a second type, which lead from bit line sense amplifiers.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: February 22, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Joon Hwang
  • Patent number: 6831869
    Abstract: In a semiconductor memory device, a redundant memory cell is accessible based on an input address signal by a redundant word line selection signal which is output in accordance with whether data read is to be performed or a memory operation other than data read is to be performed.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: December 14, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kaname Yamano
  • Patent number: 6816402
    Abstract: A write conductor layout structure for minimizing programming currents of an MRAM is disclosed. A magnetic memory cell has sense layer which is positioned between a first conductor having a width in a first direction and a second conductor having a width in a second direction. The width of the first and/or second conductor is narrower than a corresponding width of the sense layer. At least one of the first and second conductors is positioned so that the edge of the conductor extends beyond the edge of the sense layer.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: November 9, 2004
    Assignee: Micron Technology, Inc.
    Inventor: James G. Deak
  • Patent number: 6809974
    Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: October 26, 2004
    Assignee: Micron Technology, Inc.
    Inventors: William Jones, Wen Li, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller
  • Patent number: 6809977
    Abstract: A spatial light modulator comprising a memory cell array for use in display systems and a method of operating the memory cell array have been disclosed herein. The memory cell array comprises one or more rows of memory cells. Each row of memory cells is provided with a plurality of wordlines so that the memory cells in a row can be activated separately and independently. Memory cells connected to different wordlines in the same row, and the memory cells connected to different wordlines in different rows can be activated synchronized or asynchonized as desired. With is configuration, perceived artifacts, such as perceived dynamic-false-contouring artifacts, can be suppressed, if not eliminated. A row of reference memory cells can be formed within the memory cell array. The reference memory cells can maintain a predefined reference voltage state that is different from the voltage states maintained by the other memory cells of the memory cell array.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: October 26, 2004
    Assignee: Reflectivity, INC
    Inventor: Peter W. Richards
  • Patent number: 6807098
    Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: October 19, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yong Jeong, Sung-Soo Lee
  • Patent number: 6804132
    Abstract: An apparatus for reading out multiple match hits from a content addressable memory (CAM), comprising a priority encoder for receiving a plurality of matchlines from a CAM and for encoding addresses of the CAM that are associated with the matchlines that indicate a match, and a matchline mask system for selectively masking off a matchline that indicates a match from the priority encoder after the address associated with that matchline is encoded by the priority encoder.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: October 12, 2004
    Assignee: International Business Machines Corporation
    Inventors: William R. Andersen, Joseph H. Heinrich
  • Patent number: 6798688
    Abstract: A CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI) and may include fully depleted (FD) FETs. A power line supply select at each row selectively increases cell supply voltage to a full supply voltage when the row is selected. A word line decoder selects a row of cells that are provided the supply voltage and cells in remaining rows are provided a reduced supply voltage. Leakage is substantially lower in said remaining rows than in said selected row. The sense amplifier may include cross coupled FD NFETs sensing stored data. A read/write-select in each bit path selectively blocks cell writes when cell contents are not being changed. Power is not expended unnecessarily writing to cells.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: September 28, 2004
    Assignee: International Business Machines Corp.
    Inventor: Rajiv V. Joshi
  • Patent number: 6795330
    Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: September 21, 2004
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Nicolas Demange, Salvatore Torrisi, Giampiero Sberno
  • Patent number: 6795354
    Abstract: A circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof are provided. The AC-timing parameter control circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion. The control circuit compares the pulse width or period of an input signal to one or more different reference-widths pulses, with the reference width(s) set by the delay-time-defining portion and the reference pulses generated by the comparing portion. The controlling portion indicates whether the input signal width or period was less than or greater than each o the reference-width pulses. The control circuit output signals can be used to tailor the operation of the device based on a direct comparison of an AC-timing parameter to one or more reference values.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: September 21, 2004
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Jeong-Hyeon Cho, Byung-Chul Kim
  • Patent number: 6791867
    Abstract: A data storage device includes a plurality of shunt elements having controlled current paths connected in series, and a plurality of memory cells having programmable resistance states. Each memory cell is connected across the controlled current path of a corresponding shunt element.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Lung T. Tran
  • Patent number: 6788581
    Abstract: A transistor operating as a current source supplying a memory cell with a current is configured to operate in a saturation range when a node subjected to a decision as to whether a memory cell has a high or low level has a voltage in a range of no more than a threshold voltage.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Masaaki Mihara
  • Patent number: 6788574
    Abstract: A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: September 7, 2004
    Assignee: Virage Logic Corporation
    Inventors: Kim-Kwong Michael Han, Narbeh Derhacobian, Jaroslav Raszka
  • Patent number: 6785180
    Abstract: A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an integrated circuit. The two memory registers are programmed to provide two different soft-start settings for two distinct charge pump turn-on conditions, initial power-up and flash programming. Charge pump feedback logic is employed to detect the charge pump turn-on condition and activate the proper pre-programmed soft-start setting loaded in the memory registers.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Paul Cheung
  • Patent number: 6785158
    Abstract: Nonvolatile memory cells are arranged at crossing points of bit-lines and word-lines. A mode signal indicates whether the nonvolatile memory cells are to be used as a RAM or as a ROM. When the nonvolatile memory cells are to be used as RAM, current is allowed to flow through the bit-lines in one specific direction, current is allowed to flow through the word-lines and the direction of the current flowing through the word-lines is adjusted to write data in the nonvolatile memory cells. When the nonvolatile memory cells are to be used as ROM, no current is allowed to flow through the bit-lines or the word-lines so that data can not be written in the nonvolatile memory cells.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: August 31, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Hidenori Nagashima
  • Patent number: 6781904
    Abstract: This invention provides a semiconductor memory device operating at a low operating voltage (e.g., 1.8 V) and the semiconductor memory device includes a discharge circuit for discharging a voltage of a bit line prior to read/write operations. The discharge circuit includes high-voltage and low-voltage transistors coupled in series between the bit line and a reference voltage. The high-voltage transistor is switched on and off by a high voltage and the low-voltage transistor is switched on and off by a discharge signal.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: August 24, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Keun Lee, Young-Ho Lim