Abstract: According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Abstract: A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.

Abstract: A ROM system which provides for reduced size and power consumption. This ROM systems allows for inverting the programming and sensing of information in bit cells of the ROM to reduce the number of transistors in bit cells of the ROM. Further bit cells of the ROM provide that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed.

Abstract: A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.

Abstract: A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.

Abstract: A multiplexer includes a plurality of stages. Each stage includes a storage device coupled to a data output; a first diode coupled between a data input and a power supply input; and a second diode coupled between the power supply input and the data output.

Abstract: Devices and methods for enhancing decoding a non-volatile memory device are discussed. One aspect of the present invention includes a method for decoding a non-volatile memory device. The method includes decoding a set of input signals to present a row decoded signal; driving a node by a driver that receives the decoded signal; transferring a negative supply to a word line by a transfer mechanism; and limiting a rate of flow of electric charge from the negative supply to the word line so as to inhibit an undesired rate of flow of electric charge from the negative supply to the word line.

Abstract: The present invention provides a serial access memory low in current consumption, which is capable of restraining an increase in chip size even if memory capacity increases.

Abstract: A method and apparatus for performing read and write operations in matrix-addressed memory array of memory cells is described. The memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular and electret or ferroelectric material, where a logical value stored in a memory cell is represented by an actual polarization state in the memory cell. The degree of polarization in the polarizable material is limited during each read and write cycle to a value defined by a circuit device controlling the read and write operations, with said value ranging from zero to an upper limit corresponding to saturation of the polarization and consistent with predetermined criterta for a reliable detection of a logic state of a memory cell.

Abstract: A circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The circuit includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.

Abstract: The invention relates to a configuration for fuse initialization, in which the fuse initialization signals bFPUP, FPUN are carried on a total of two lines to the individual fuse banks, and are sent back with a time delay.

Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.

Abstract: A non-volatile semiconductor memory device includes a first memory bank, a second memory bank, a first power supply circuit, and a second power supply circuit. In write operation, the first power supply circuit supplies a boosted voltage to the first memory bank, and the second power supply circuit supplies a boosted voltage to the second memory bank. This enables sufficient current supply capability to be assured. On the other hand, in read operation, only the second power supply circuit supplies a boosted voltage to the first and second memory banks. This enables reduction in power consumption.

Abstract: The present invention provides a semiconductor device such as a multi-valued flash memory or the like, which is capable of shortening a processing time required to set write control information to a sense latch. The semiconductor device is capable of electrically writing multi-value information therein. Bit lines are connected to the right and left input/output terminals of a sense latch, and data latches are connected to the respective bit lines. A decoder is provided which decodes write data supplied from outside to thereby generate write control information. The write control information is latched in each of the sense latch and data latches, and the latched control information is set as information indicative of go/no-go of the application of a write voltage, which corresponds to each value in a multivalue.

Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The circuit includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.

Abstract: First of all, bit lines and sense amplifier nodes are precharged separately. Thereafter, the precharged state of the bit lines is canceled, and the gate level of each charge transfer transistor is raised to an appropriate value while the sense amplifier nodes are maintained in the precharged state, thereby copying the threshold voltage difference between the charge transfer transistors as the potential difference between the pair of bit lines. The precharged state of the sense amplifier nodes is then canceled, and the gate level of the charge transfer transistor is raised to an appropriate value, thereby reading out data from the memory cell to the sense amplifier nodes.

Abstract: An improved memory device employs a DRAM array for data storage. In the device, a special row address decoder simultaneously asserts a corresponding unique pair of the wordlines in response to each received valid row address, so that a single valid row address simultaneously accesses two rows of memory cells in the array. The device differentially writes and reads each bit of data across a pair of memory cells; each one of the pair of memory cells being within a different respective row of the array, and the two different rows together corresponding to one of the unique pairs of wordlines asserted by the row address decoder responsive to a valid row address. This arrangement obviates the need for high voltage boosting circuits and thereby reduces power consumption.

Abstract: A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.

Abstract: A semiconductor integrated circuit, includes a first macro and a second macro. The first macro outputs a data signal. The second macro inputs the data signal. The first macro fixes the data signal at a non-high level state that is not a high level in response to a control signal.