Abstract: A DRAM includes a test mode circuit. Test mode circuit generates respective test mode signals of an L level and an H level by detecting first and second power supply voltages in response to first and second test mode shift signals, respectively. A control circuit controls peripheral circuits to input and output data for executing a special test to and from a plurality of memory cells in response to receiving of the test mode signals of an L level and an H level. Consequently, a semiconductor memory device can enter the test mode in a module.

Abstract: A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input circuit is coupled to the one or more defective memory columns.

Abstract: A ternary content addressable memory device is disclosed which writes data into a data cell and writes mask data into a mask data cell in a ternary CAM cell unit by a single write cycle when the ternary content addressable memory device is used as a binary content addressable memory device. The content addressable memory device includes at least the ternary content addressable memory cell unit which stores ternary data representing three states of “0”, “1”, and “don't care”. The ternary content addressable memory cell unit include the data cell for storing binary data of “0” and “1”, and the mask cell for storing mask data for masking the binary data from a searching operation.

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract: A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.

Abstract: A magnetic memory includes a memory cell and a conductor wherein the memory cell is crossed by the conductor. A write pulse generator is coupled to the conductor and is configured to provide a discharge current to the conductor during a write operation of the memory cell.

Abstract: A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.

Abstract: An MRAM device includes an array of memory cells. A plurality of traces cross the memory cells. An address decoder coupled to the plurality of traces decodes an address and selects a corresponding subset of the traces. A sparing circuit coupled to the address decoder receives a logical address and outputs a physical address to the address decoder based on memory cell defect information.

Abstract: An apparatus for reading a ROM device. A ROM memory cell's value is determined by comparing the output current from the circuit with a reference current. The output current from a memory cell is outputted to a current conveyor with a reference current and then inputted to a difference sense amplifier which compares the output current with the reference current and amplifies the difference. If a memory cell is programmed the transistor in the memory cell will draw current away from the current source reducing the output current. This will cause the programmed memory cell current to be of a lesser value than a reference current. If a memory cell has been programmed the transistor will not draw any current and therefore the output current will be a greater value than the reference current. Two extra transistors can be added to adjust the current level on reference bitline.

Abstract: A method of using an integrated circuit with at least one defect, said method comprising the steps of determining the location of one or more defects in said integrated circuit; selecting a program to be stored on said integrated circuit, said program being selected on the basis of the location of said one or more defects; and loading said program onto said integrated circuit.

Abstract: In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.

Abstract: A non-volatile memory unit includes memory units for providing a data current corresponding to stored data; a first load unit having a first end; a second load unit having a second end; and a sensing unit. The first load unit and the second load unit can receive current input to build voltages respectively at the first end and the second end. When the memory unit provides the data current, the second load unit is enabled such that the data current inputs into the first load unit and the second load unit; then the second load is disabled after a predetermined time such that the data current inputs into the first load unit only, and the sensing unit generates a data signal for data-acquisition according to a voltage difference between the voltage at the first end and a reference voltage.

Abstract: The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.

Abstract: A structure of a flash memory device. The flash memory comprises a deep n-well formed in a substrate, a p-well in the deep n-well, a stacked gate structure on the substrate, source and drain regions in the substrate at two respective sides of the stacked gate, an n-well extending from the drain region to a position under the stacked-gate structure, an n− pocket doped region under the stacked-gate structure and connected between the n-well and the source region. The flash memory uses avalanche induced hot electron injection for programming, and the F-N tunneling effect to perform erase operation.

Abstract: A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.

Abstract: A method for reducing programming time of a nonvolatile semiconductor device is provided. In the method, after a plurality of memory cells are programmed by n-bit units, the memory cells are checked to determine whether the programming is completed. If any memory cell fails the programming operation, the reprogramming of the memory cells are performed. For the reprogramming, the n is multiplied by 2, wherein n is an integer not less than 2. Otherwise, if all the memory cells complete the programming or the number of the program operation gets to the maximum value, the memory cells finish the program operation. Accordingly, the method can reduce time for programming of the memory cells.

Abstract: A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

Abstract: A synthetic ferrimagnet reference layer for a magnetic storage device. The reference layer has first and second layers of magnetic material operable to be magnetized in first and second magnetic orientations. A spacer layer between the layers of magnetic material is of suitable dimensions to magnetically couple the magnetic layers in opposite directions. The layers of magnetic material have substantially the same coercivities.

Abstract: In an IC having memory cells, a write operation is performed on a word within a particular row of memory cells. The other words within the same row are refreshed during the same cycle. In another embodiment, dual port memory cells are employed to enable a second row of memory cells to be refreshed during the same cycle.

Abstract: A specific row of memory cells in a flash memory is set to be in a lock mode state, which affects reading of data in other rows of memory cells in a common memory array. Thus, a flash memory having a data concealing function is achieved.