Abstract: This invention provides a semiconductor memory device operating at a low operating voltage (e.g., 1.8 V) and the semiconductor memory device includes a discharge circuit for discharging a voltage of a bit line prior to read/write operations. The discharge circuit includes high-voltage and low-voltage transistors coupled in series between the bit line and a reference voltage. The high-voltage transistor is switched on and off by a high voltage and the low-voltage transistor is switched on and off by a discharge signal.

Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

Abstract: An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.

Abstract: The present memory includes a plurality of transistors laid out in a number of rows and columns. First and second series-connected transistors are included in a first column, and are connected between first and second bit lines and are respectively associated with first and second word lines. A region between the series-connected first and second transistors is connected to a first bit line. Third and fourth series-connected transistors are included in a second column, and are connected between the second bit line and a third bit line and are respectively associated with third and fourth word lines. A region between the series-connected third and fourth transistors is connected to a second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors.

Abstract: Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines.

Abstract: An integrated circuit contains a static memory cell with a pair of cross-coupled inverters. The outputs of the inverters are coupled to bitlines the main current channels of access transistors. The integrated circuit operates in a normal mode and in a test mode. In the test mode the conductivity of the access transistors is made relatively higher in proportion to the drive strength of the memory cell while substantially equal voltages are applied to the bitlines (for example by applying a voltage to the wordline that makes the access transistors more conductive than during access in the normal mode). An error is detected when this causes the state of the cell to flip.

Abstract: A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.

Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

Abstract: A driver circuit transmits a signal to a receiver circuit through a signal transmission line. The driver circuit has an output driver, a front driver, and a level adjuster. The front driver drives the output driver, and the level adjuster adjusts the output level of the front driver. The output driver generates a signal whose level is variable in response to an output level of the front driver.

Abstract: A DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency from the first and second internal clocks on the basis of an internal signal. A repeater recovers signal levels of the third and fourth internal clocks and outputs the third and fourth internal clocks as DLL clocks. The data output circuit takes in read data using the DLL clocks outputted from the repeater, and outputs the read data to an outside in a half cycle synchronously with the DLL clocks. In this way, a circuit area of a semiconductor memory device can be reduced by generating the DLL clocks in a prior stage to the data output circuit.

Abstract: A system and memory including a circuit for setting write latency and a write/valid indicator. Time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. A write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

Abstract: A semiconductor memory device which is capable of selectively performing different functions has a chip having a nonvolatile memory capable of rewriting stored data, and a mode switcher disposed on the chip for irreversibly inhibiting data from being written in the nonvolatile memory upon elapse of a preset period of time from a time when a power supply of the semiconductor memory device is turned on if a predetermined signal is not supplied from outside of the chip within the preset period of time.

Abstract: A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.

Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.

Abstract: A magnetic memory device includes a plurality of word lines extending into a first direction, a plurality of bit lines extending into a second direction, and a plurality of magnetic memory cells which are provided at intersections of the word lines and the bit lines. Each of the memory cells includes a ferromagnetic film. Data is written in a first one of the magnetic memory cells with a synthetic magnetic field generated by first current flowing on a specific word line associated with the first magnetic memory cell and second current flowing on a specific bit line associated with the first magnetic memory cell.

Abstract: A program unit includes two program cells having an electric resistance varying according to a magnetization direction thereof. These program cells are magnetized in the same direction in initial state, that is, non-program state. In program state, the magnetization direction of one of the program cells selected according to program data is changed from the initial state. One-bit program data and information of whether the program unit stores program data or not can be read based on two program signals generated according to the electric resistances of the two program cells.

Abstract: As soon as a write command is input to a nonvolatile memory cell array, an internal charge pump circuit starts pumping. When the pumping is achieved, the writing to the nonvolatile memory cell array is implemented. By keeping the internal charge pump circuit ready for a next write command even after the end of the first write operation, it is possible to cut down the time required for the activation/deactivation of the internal charge pump circuit, which would cause redundancy. When it is determined that no successive write operations are to be performed, the internal charge pump circuit is deactivated. Similar controls are carried out for the other commands which rewrite the contents of the nonvolatile memory cell array.

Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

Abstract: A semiconductor memory device including a plurality of cell arrays (121 to 128) and a plurality of sense amplifier sections is disclosed. Adjacent cell arrays may have a sense amplifier section disposed between. Sense amplifiers (131 to 163) within a sense amplifier section may be connected to a bit line that is connected to a plurality of memory cells in more than one of the cell arrays (121 to 128). When a cell array (123) is activated, sense amplifier sections that may be distributed around edges of a plurality of cell arrays (122 to 124) may be activated to sense data from the activated cell array (123). In this way, current may be distributed and noise may be reduced. An activated bit line (227) may be adjacent to a precharged bit line (250) in a non-activated cell array (124). In this way, cross-talk between activated bit lines may be reduced.

Abstract: A static memory device that utilizes differential current bit line drivers to write information into the device's memory cells, and differential current sensing read amplifiers to read information from the cells. The drivers and amplifiers operate using limited differential current. The use of limited differential current, as opposed to voltages, reduces the power consumed by the device and increases the speed of read and write operations.