Abstract: Provided herein may be a semiconductor memory device, a controller, and a memory system having the same. By means of a method of operating the controller of the memory system, the semiconductor memory device, which is included in the memory system and including a plurality of memory blocks, is controlled. The method of operating the controller may include sensing a power-on state of the memory system, and performing an erased block scan operation on the plurality of memory blocks using a scan read voltage, based on sensing that the memory system is in the power-on state. Each of memory cells in the plurality of memory blocks may store at least two bits of data, and the scan read voltage may enable an erase state and a program state of the memory cells to be distinguished from each other.

Abstract: Apparatuses and methods for providing data from stacked memory are described. The stacked memory may include multiple die. In some examples, a master die may receive data from one or more slave die. The master die may provide data from the master die and the data from the one or more slave die to a plurality of output terminals. Different ones of the output terminals may provide data from a different die of the stacked memory. In some examples, the data may be retrieved from the multiple die concurrently.

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

Abstract: A memory device including: a memory cell array including a plurality of memory cell rows; an address buffer configured to store addresses of target rows of the plurality of memory cell rows, wherein the addresses of the target rows have been repeatedly accessed; a minimum access output circuit configured to select, when there are a plurality of rows having a same minimum access count among the target rows, any one of the plurality of rows having the same minimum access count as a minimum access row based on a selection command value, and to output an index value of the minimum access row; and a control circuit configured to output a command instructing replacement of an address corresponding to the index value of the minimum access row with an address of an access row and storage of the address of the access row in the address buffer.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

Abstract: A semiconductor device includes a base substrate comprising a first region and a second region, a photonics device disposed in the first region, the photonics device comprising a first doped layer disposed on the base substrate, and a second doped layer disposed on the first doped layer so that at least a portion vertically overlaps the first doped layer, the second doped layer having a first vertical thickness, and a transistor disposed in the second region, the transistor comprising a semiconductor layer disposed on the base substrate and horizontally spaced apart from the first doped layer, and a gate electrode horizontally spaced apart from the second doped layer and disposed on the semiconductor layer, disposed at the same vertical level as that of the second doped layer, and having a second vertical thickness equal to the first vertical thickness.

Abstract: In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.

Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

Abstract: A method of erasing vertical NAND strings from a source side of the vertical NAND strings includes applying a relatively high erase voltage to a source line, applying a relatively low voltage or 0 V to bit lines, applying a first drain-select-level voltage that is less than the erase voltage to one of the first drain-select-level electrically conductive layers, and applying a second drain-select-level voltage that is greater than the first drain-select-level voltage and not greater than the erase voltage to one of the second drain-select-level electrically conductive layers.

Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

Abstract: A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

Abstract: A storage device includes a power supply circuit that receives a power disable signal from a host device and provides a first internal voltage and a second internal voltage, a non-volatile memory including a memory device, and a storage controller that controls the non-volatile memory and includes a processor that performs a data recovery operation on data stored in the memory device and a host interface that communicates with the host device. When the power disable signal is activated at a power off time, the storage controller is powered off, the power supply circuit interrupts the first internal voltage and the second internal voltage during a reference time following the power off time, and provides the first internal voltage to the processor after the reference time has elapsed following the power off time.

Abstract: Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.

Abstract: A memory system includes a non-volatile memory, and a controller configured to issue a first command requesting a first operation to the non-volatile memory and a second command to the non-volatile memory. The second command may be for requesting a duration time of the first operation or for requesting an execution stage of the first operation. In accordance with the information returned by the non-volatile memory in response to the second command, the controller issues a third command requesting a completion status of the first operation to the non-volatile memory. The first operation may be a data read operation, a data write operation, or a data erase operation.

Abstract: A controller for controlling a memory device comprising a plurality of multi-level cell memory blocks, the controller includes: a processor suitable for controlling the memory device to perform a read operation on a target logical page using some of the plurality of read voltages in a selected read voltage set; and an error correction code (ECC) component suitable for determining whether the read operation is successful, by performing error detection and correction on data generated in the read operation and output from the memory device, wherein, when the read operation is determined to be successful, the processor updates the selected read voltage set with the read voltages used in the read operation when it is successful and estimated values of unused read voltages of the selected read voltage set, the estimated values being determined based on the used read voltages.

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

Abstract: Shift register includes input sub-circuit coupling input terminal to first node responsive to signal of first clock terminal in input stage, control sub-circuit transmitting signal of second clock terminal to intermediate output terminal according to level at first node and controlling potential of third node according to potential of intermediate output terminal and signal of third clock terminal in input, output and reset stages, pull-up sub-circuit coupling second level terminal to final output terminal responsive to potential of intermediate output terminal in output stage, first voltage stabilization sub-circuit stabilizing voltage between final output terminal and third node responsive to signal of next-stage node connection terminal, pull-down transistor having gate electrode coupled to third node, first electrode coupled to first level terminal, and second electrode coupled to final output terminal.

Abstract: The present technology relates to an electronic device. A storage device in which a memory device controls an ODT operation to improve operation performance of the memory device with a small number of pins includes a plurality of memory devices comprising a target memory device in which an operation is performed and non-target memory devices, and a memory controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes an on die termination (ODT) flag generator configured to generate a flag that indicates that an ODT operation is possible for the non-target memory devices, and an ODT performer configured to determine whether the ODT operation is an ODT read operation for a read operation or an ODT write operation for a write operation based on the flag and configured to generate an enable signal that enables the ODT read operation or the ODT write operation.

Abstract: A method for performing memory access management with aid of machine learning in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: in the memory device, during a training phase, performing machine learning according to a predetermined database regarding threshold voltage distribution, to generate at least one threshold voltage identification model, wherein the at least one threshold voltage identification model is utilized for determining bit information read from a memory cell of the NV memory; and in the memory device, during an identification phase, obtaining representative information of one or more reference voltages when reading the NV memory, for performing machine identification according to the at least one threshold voltage identification model to generate read data, wherein the read data includes the bit information.