Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

Abstract: A semiconductor memory device may include a plurality of memory cells wherein identifiers may be provided to the memory cells. The semiconductor memory device may include a first circuit, a second circuit and a power control circuit. The first circuit may include a first power terminal and a second power terminal. The second circuit may include a third terminal and a fourth terminal. The power control circuit may be configured to apply a first power voltage or a ground voltage to the first power terminal and to apply the ground voltage to the second power terminal based on the identifiers.

Abstract: A memory device is provided, including an array of bit cells and a set of tracking cells. The set of tracking cells is arranged adjacent to the array of bit cells along a first direction. The set of tracking cells includes a set of first tracking cells configured to perform a read tracking operation and a set of second tracking cells configured to perform a write tracking operation and arranged adjacent to the set of first tracking cells along a second direction. First tracking cells in the set of first tracking cells are coupled in series with each other and arranged along the second direction, and second tracking cells in the set of second tracking cells are coupled in series with each other and arranged along the second direction.

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.

Abstract: Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.

Abstract: A non-volatile memory includes a memory cell having a first transistor and a second transistor, a driving circuit arranged to apply a read voltage to gates of the first and second transistors, and a signal output circuit arranged to output a signal associated with a first value or a signal associated with a second value, based on drain currents of the first and second transistors, in a read operation in which the read voltage is applied. The second transistor is constituted of a parallel circuit of a plurality of unit transistors, and gate width of each of the unit transistors is larger than that of the first transistor.

Abstract: Methods and apparatus for duty cycle adjuster optimization training algorithms to minimize jitter associated with DDR5 DRAM transmitters. Basic and Advanced Duty Cycle Adjuster (DCA) training algorithms are implemented to reduce duty cycle error and hence reduce phase mismatch translated jitter in the transmitter DQS signals. In accordance with aspects of the Basic DCA training algorithm, duty cycles for QCLK, IBQCLK, and QBCLK are adjusted by a memory controller that utilizes a DCA function implemented on a memory module (e.g., DDR5 SDRAM DIMM) to obtain a first set of optimized DCA code settings. The first set of optimized DCA code settings are then used as initial settings for the Advance DCA training algorithm to further optimize the DCA code settings for QCLK, IBQCLK, and QBCLK. A similar technical may be employed to reduce duty cycle error and jitter for DQ signals.

Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A semiconductor device includes a memory bank and first and second clock generators. The first clock generator includes a first transistor configured to receive an external clock signal. The first clock generator is configured to generate a global clock signal that is based on the external clock signal and that controls writing to and reading from the memory bank. The second clock generator includes a first transistor configured to receive the external clock signal. The second clock generator is configured to generate a pipeline clock signal that is based on the external clock signal and that controls a pipeline operation of reading from the memory bank. Methods of operating the first and second clock generators are also disclosed.

Abstract: An amplification circuit includes: a sense amplification circuit including a read node, a complementary read node, a first node and a second node; an isolation circuit, which couples the read node to a bit line and couples the complementary read node to a complementary bit line in a sense amplification stage; an offset cancellation circuit, which couples the bit line to the complementary read node and couple the complementary bit line to read node in an offset cancellation stage; and a first power supply circuit, coupled to the first node, including a first power supply and a second power supply, a power supply voltage of the first power supply being higher than that of the second power supply, the first power supply circuit couples the first power supply to the first node in offset cancellation stage, and couples the second power supply to the first node in sense amplification stage.

Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

Abstract: An integrated circuit includes a sampling control circuit configured to: generate a counting signal according to a periodic signal during a sampling period, and generate a plurality of sampling enable signals by comparing counting bits of the counting signal with random bits of a random signal; and a sampling circuit configured to: store an input address as a plurality of sampling addresses according to the respective sampling enable signals, and generate a plurality of valid section signals based on the sampling enable signals to output one of the sampling addresses as a target address according to an uppermost valid section signal among activated valid section signals.

Abstract: A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.

Abstract: An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.

Abstract: The invention is notably directed to a method of programming memory elements of an in-memory computing (IMC) device. The IMC applies a SET signal to the K memory elements of said each cell to set each of the K memory elements to a SET state and reading K conductance values of the K memory elements in the SET state. The IMC adjusts, based on the K conductance values read and the target conductance value, a conductance value of at least one of the K memory elements to match a summed conductance of the K memory elements of said each cell with the target conductance value. The IMC maximizes a number of the K memory elements that are either in their SET state or in a RESET state of zero conductance nominal value, such that at most one of the K memory elements is neither in a SET state nor in a RESET state.

Abstract: A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes the following. A reading operation is performed on each of a plurality of programmed memory cells of the memory device. Whether a charge loss phenomenon occurs in the programmed memory cells is determined through the reading operation to set the programmed memory cells to be charge loss memory cells. A refill program operation is performed on the charge loss memory cells.

Abstract: In one example, a peripheral circuit in a die is configured to: first, receive control commands, and generate indication information according to the control commands, the control commands being used for indicating the die to determine the address of the die, the indication information being used for indicating M dies to share the same enable pin, M being a positive integer greater than or equal to 1; and then, determine the address of the die according to the indication information, and send the address of the die, the address being used for addressing an enable signal provided by the enable pin.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.