Patents Examined by Thong Q. Le
  • Patent number: 11908514
    Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage config
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 20, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SAS
    Inventors: Antonino Conte, Alin Razafindraibe, Francesco Tomaiuolo, Thibault Mortier
  • Patent number: 11908533
    Abstract: Disclosed is an operation method of a memory device which includes floating a first driving line corresponding to a first word line from the first word line and precharging the first driving line with a first voltage, floating the first driving line from the first voltage to sense a first voltage variation of the first driving line, storing the first voltage variation in a first capacitor, electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage, floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line, and outputting a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation and the second voltage variation.
    Type: Grant
    Filed: April 24, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyunkook Park
  • Patent number: 11900997
    Abstract: Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John F. Schreck, George B. Raad
  • Patent number: 11901008
    Abstract: A three-dimensional flash memory is disclosed. According to one embodiment, the three-dimensional flash memory has a structure in which a boosting area is reduced, a structure to which a small block is applied, a structure to which a COP is applied and in which a wiring process is simplified, or a structure to which symmetrical U-shaped BiCS are applied.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yunheub Song
  • Patent number: 11887668
    Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and applies, during a first time period of the program operation, a ramping wordline voltage to a set of wordlines associated with the memory array. The control logic causes, during the first time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and ground voltage, wherein each pillar corresponds to a programming level of a set of programming levels. The control logic further causes, during a second time period of the program operation, a set of programming pulses to be applied to the set of memory cells, wherein each programming pulse of the set of programming pulses programs each programming level of the set of programming levels associated with the identified set of memory cells.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sheyang Ning, Lawrence Celso Miranda
  • Patent number: 11887643
    Abstract: A magnetic shielding structure for protecting an MRAM array from adverse switching effects due to external magnetic fields of neighboring devices is provided. The magnetic shielding structure includes a bottom magnetic shield material-containing layer and a top magnetic shield material-containing layer within the MRAM array. The bottom and top magnetic shield material-containing layers can be connected by a vertical magnetic shield containing-material layer that is located near each end of the bottom and top magnetic shield material-containing layers. The bottom magnetic shield material-containing layer is located beneath a MTJ pillar of each MRAM device, but above, bottom electrically conductive structures that are in electrical contact with the MRAM devices. The top magnetic shield material-containing layer is located above the MRAM devices, and is located laterally adjacent to, but not above or below, top electrically conductive structures that are also in electrical contact with the MRAM devices.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Dimitri Houssameddine, Kangguo Cheng, Ruilong Xie
  • Patent number: 11880602
    Abstract: A data writing method includes: receiving a write command, where the write command carries a type of to-be-written data; determining, based on the type of to-be-written data, a type of storage area that is in an SSD and into which the to-be-written data is written, where the SSD includes a plurality of types of storage areas; determining, based on the type of storage area, a target storage area into which the to-be-written data is written; and writing the to-be-written data into the target storage area. In embodiments of this application, data processing efficiency can be improved.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: January 23, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Meng Zhou, Jianhua Zhou
  • Patent number: 11880585
    Abstract: Embodiments relate to a semiconductor memory and a method for writing data. The semiconductor memory includes: at least one storage array, the storage array including a plurality of data storage units and a plurality of check bit storage units; a check module, configured to receive written data and generate check data according to the written data; and a data transmission module, respectively connected to the check module and the storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units. A first transmission time duration of the check data is shorter than a second transmission time duration of the written data.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: January 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Hongwen Li, Kangling Ji
  • Patent number: 11875844
    Abstract: Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Inhak Lee, Sang-Yeop Baeck, Younghwan Park, Jaesung Choi
  • Patent number: 11868650
    Abstract: Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first emphasized characteristic and a second memory circuit having a second emphasized characteristic. The first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 11861236
    Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kalyan Chakravarthy C. Kavalipurapu, Chang H. Siau, Shigekazu Yamada
  • Patent number: 11861237
    Abstract: A storage device includes a nonvolatile memory device having a plurality of memory cells and a storage controller. Each memory cell is set to one of a plurality of memory cell states, wherein distinct subsets of the memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in one of the memory cells in a first state, performs a multiplier-accumulator (MAC) operation on the data, and sets the one memory cell to a second state corresponding to a result of the MAC operation to perform an in-place update.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hyun Kim, Jong-Hoon Lee
  • Patent number: 11854589
    Abstract: A magnetoresistive element comprises a nonmagnetic sidewall-current-channel (SCC) structure provided on a surface of the SOT material layer that exhibits the Spin Hall Effect, which is opposite to a surface of the SOT material layer where the magnetic recording layer is provided, and comprising an insulating medium in a central region of the SCC structure, and a conductive medium being a sidewall of the SCC structure and surrounding the insulating medium, making an electric current crowding inside the SOT material layer and the magnetic recording layer to achieve a spin-orbit torque and a higher spin-polarization degree for an applied electric current.
    Type: Grant
    Filed: October 24, 2021
    Date of Patent: December 26, 2023
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Patent number: 11837287
    Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
  • Patent number: 11830549
    Abstract: Disclosed are a method of operating a selector device, a method of operating a nonvolatile memory apparatus to which the selector device is applied, an electronic circuit device including the selector device, and a nonvolatile memory apparatus. The method of operating the selector device controls access to a memory element, and includes providing the selector device including a switching layer and first and second electrodes disposed on both surfaces of the switching layer, which includes an insulator and a metal element, and applying a multi-step voltage pulse to the switching layer via the first and second electrodes to adjust a threshold voltage of the selector device, the multi-step voltage pulse including a threshold voltage control pulse and an operating voltage pulse. The operating voltage pulse has a magnitude for turning on the selector device, and the threshold voltage control pulse has a lower magnitude lower than the operating voltage pulse.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 28, 2023
    Assignees: SK hynix Inc., Industry-University Cooperation Foundation Hanyang University ERICA Campus
    Inventors: Tae Jung Ha, Soo Gil Kim, Jeong Hwan Song, Tae Joo Park, Tae Jun Seok, Hye Rim Kim, Hyun Seung Choi
  • Patent number: 11823755
    Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Alberto Troia
  • Patent number: 11818890
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: November 14, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Go Oike, Tsuyoshi Sugisaki
  • Patent number: 11816357
    Abstract: Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Anthony D. Veches, Brian P. Callaway
  • Patent number: 11810609
    Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Efrem Bolandrina, Ferdinando Bedeschi
  • Patent number: 11804832
    Abstract: Embodiments herein relate to protection of a standby amplifier of a memory device. Specifically, an input voltage of the standby amplifier may be reduced to decrease an occurrence of damage to the standby amplifier or components thereof. In some embodiments, the input voltage may be reduced using a voltage divider that provides the reduced input voltage to the standby amplifier during a power up operation. Upon completion of the power up operation, the input voltage of the standby amplifier may return to an operating voltage. The reduced input voltage may reduce the occurrence of damage to the standby amplifier by maintaining a gate to drain voltage of one or more transistors of the standby amplifier below a maximum.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mishal Kumar, Wei Lu Chu