Abstract: An operating method of a controller includes transmitting an extended status check command to a nonvolatile memory device, toggling a read activation signal /RE to correspond to the number of planes inside the nonvolatile memory device, after transmitting the extended status check command, and receiving status information of planes of the nonvolatile memory device through data lines according to a data strobe signal DQS corresponding to the read activation signal /RE.

Abstract: A magnetic multilayer film for a magnetic memory element includes an amorphous heavy metal layer having a multilayer structure in which a plurality of first layers containing Hf alternate repeatedly with a plurality of second layers containing a heavy metal excluding Hf; and a recording layer that includes a ferromagnetic layer and that is adjacent to the heavy metal layer, the ferromagnetic layer having a variable magnetization direction.

Abstract: According to one embodiment, a magnetic memory device includes a first wiring line, a plurality of second wiring lines, a plurality of first memory cells each including a first magnetoresistance effect element and a first selector connected in series, and a first switch. A respective one of the first memory cells is connected between the first wiring line and a respective one of the second wiring lines, a first voltage is applied to the second wiring line connected to a selected first memory cell, and a second voltage is applied to the second wiring line connected to a non-selected first memory cell, a first terminal of the first switch is connected to the first wiring line, and a third voltage is applied to a second terminal of the first switch.

Abstract: A reference voltage generation device includes a noise information generation circuit configured to generate power noise information based on a first power noise and a second power noise, the first power noise and the second power noise generated based on a first power and a second power supplied to a first electronic device and propagated from the first electronic device to a second electronic device through a communication line, and the first electronic device and the second electronic device configured to perform data communication using a multi-level signaling scheme. The device includes a reference voltage generation circuit configured to generate three or more reference voltages for the multi-level signaling scheme based on the power noise information, and the second electronic device is configured to use the three or more reference voltages.

Abstract: A semiconductor device includes: a memory test circuit that outputs a fourth signal based on a logic level of a second signal corresponding to a first signal output by a host and a logic level of a third signal; a memory device that becomes active or inactive based on a logic level of the fourth signal; and a test logic that outputs the third signal and performs a retention test on the memory device based on the logic level of the second signal.

Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a first circuit which controls the plurality of bit lines according to first data, a source line commonly connected to first ends of the plurality of bit lines, and a second circuit which is connected to the source line and which detects second data according to a current amount in the source line.

Abstract: A signal processing apparatus and a signal processing method are provided. The signal processing apparatus includes a memristor array, an input circuit, a first switching circuit, a second switching circuit, an output circuit, and a control circuit. The memristor array includes memristor units and is connected to source lines, word lines and bit lines. The control circuit is configured to control the first switching circuit to select at least one source line to apply at least one first signal to the at least one source line respectively, control the second switching circuit to select and activate at least one word line to apply the at least one first signal to a memristor unit corresponding to the at least one word line, and control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: A memory device includes an eFuse cell array in which unit cells of different types are alternately disposed, and each of the unit cells of different types includes a PN diode, a first NMOS transistor, and a fuse, wherein a first type unit cell and a second type unit cell are connected to each other through a common node, and the first type unit cell and the second type unit cell are disposed in a bilaterally symmetrical structure with respect to the common node.

Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N?1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

Abstract: A semiconductor memory device includes a command address control circuit configured to generate an error correction command and selection address for executing an error correction operation by receiving an external control signal, an error flag generation circuit configured to correct an error of data corresponding to the selection address and configured to generate a target error flag based on a pattern of the error of the data, and an error information processing circuit configured to generate a target address that is used as the selection address based on the target error flag in a target error correction operation that is executed based on the error correction operation.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a laminate structure arranged on the substrate and including first semiconductor layers spaced apart from each other in a direction perpendicular to a top surface of the substrate, each first semiconductor layer including channel areas spaced apart from each other in a first direction, and first doped areas and second doped areas, each first doped area being arranged on one side of a respective one of the channel areas in a second direction, each second doped area being arranged on another side of the respective one of the channel areas in the second direction; and a word line structure including word lines extending in the first direction, an edge of each word line being flush with an edge of a respective one of the channel areas in the second direction.

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a first transmission line and a second transmission line located over one another. A via is shown connecting the first transmission line and a second transmission line wherein a first side of the via and a side of the second transmission line are coplanar. A via is also shown connecting the first transmission line and a second transmission line wherein the second transmission line tapers downward from a line width to a via width.

Abstract: An IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.

Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.

Abstract: In some examples, a memory device includes a plurality of rows of memory cells, a plurality of victim counters associated with respective rows of memory cells of the plurality of rows of memory cells, and a plurality of aggressor counters associated with the respective rows of memory cells. A first victim counter of the plurality of counters is associated with a first row of the plurality of rows of memory cells, the first victim counter to advance in response to advances in counts of aggressor counters associated with neighboring rows of memory cells that are neighbors of the first row.

Abstract: A refresh circuit selects a candidate bank for refreshing from various banks of a dynamic random access memory (DRAM). Initially, the refresh circuit checks if any bank is idle (e.g., is not targeted for memory operations). If two or more banks are idle, the candidate bank is selected based on a count of accesses targeted to each occupied bank and bank-pair distances between each pair of idle and occupied banks. Conversely, if all banks are occupied, the refresh circuit selects the candidate bank based on a count of data accesses targeted to each bank and/or a count of parity accesses targeted to each bank. Each data access has the same type as that scheduled for execution on the DRAM. Once the candidate bank is selected, the refresh circuit triggers the refresh of the candidate bank.