Abstract: Provided are devices and methods relating to temperature control in a solid state drive (SSD). One embodiment include a SSD including a housing including a plurality of sides surrounding an interior region. The SSD includes at least one vent on the housing, the at least one vent configured to be opened and closed in response to a signal. The SSD also includes a temperature sensor and a controller, the controller configured to send a signal to open the at least one vent when a temperature sensed inside the interior region reaches a first temperature, and the controller configured to close the at least one vent when a temperature sensed inside the interior region reaches a second temperature, wherein the first temperature is greater than the second temperature. Other embodiments are described and claimed.

Abstract: According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.

Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device and the host device can include control logic that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.

Abstract: A memory array and its operation method are provided. The array includes plural sets of word lines; plural bit lines; and plural memory cell each arranged at intersection of the plural sets of word lines and the plural bit lines. Each memory cell has first and second conductive filament component and a switch circuit, and one ends of the first and the second conductive filament components are coupled to corresponding bit lines and the other ends thereof are coupled to the switch circuit. In the differential mode, read is performed based on the reading currents of the first and the second conductive filament components. In the single-ended mode, read is performed based on a reference current and a reading current of the first or the second conductive filament component that is formed successfully.

Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Abstract: Methods, systems, and devices for receive-side crosstalk cancelation are described. A device that receives multiple signals over different transmission lines may include a circuit for canceling crosstalk. The circuit may include one or more capacitors or inductors that are coupled with the inputs of multiple receive circuits. The circuit may also include a set of resistors that are coupled with the receive circuits. In some cases, the device may dynamically configure the cancelation circuit to provide a particular bandwidth or strength of cancelation. In such cases, the device may configure the circuit autonomously or based on control information from another device.

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

Abstract: A liquid discharge head having an element board including an element configured to discharge a liquid includes a first storage element and a second storage element. The first storage element is a fuse element or an anti-fuse element. The second storage element is a semiconductor memory capable of holding a larger capacity than the first storage element. The second storage element is provided on an area other than the element board.

Abstract: A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.

Abstract: An apparatus with a memory array having a plurality of memory cells. The apparatus also including a memory built-in self-test circuit to test the memory array. The memory built-in self-test circuit includes one or more processing devices to write a data pattern to one or more memory cells to be tested in the memory array, pause for a time period corresponding to a predetermined pause time setting, and read the written data pattern from the one or more memory cells after the time period has elapsed. The predetermined pause time setting is automatically adjusted based on memory device conditions, which can include the temperature of the apparatus.

Abstract: Methods, systems, and devices for quick activate for memory sensing are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a testing procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received activate command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received activate command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

Abstract: The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 M?, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

Abstract: The invention provides a multi-die stacked package memory and an output synchronization method thereof. The multi-die stacked package memory includes multiple dies (100), and the multiple dies (100) are stacked and packaged together to form a stacked package structure. The multiple dies (100) share a CS #pin, and the CS #pin is configured to turn on or turn off the stacked package structure. The multiple dies (100) also share an IO pin. Each die (100) is provided with a SYNC_PAD pin. The SYNC_PAD pins of the multiple dies (100) are electrically connected together, the SYNC_PAD pins are configured to judge whether the multiple dies (100) are all in an idle status or not. The multi-die stacked package memory and the output synchronization method thereof are simple in structure, easy to realize, stable and reliable.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.

Abstract: A method for regulating the memory includes operations as follows. A mapping relationship among temperatures of a transistor, body bias voltages of the transistor, and data writing time of the memory is acquired, a current temperature of the transistor is acquired, the body bias voltage is regulated based on the current temperature and the mapping relationship, to enable the data writing time corresponding to the regulated body bias voltage to be within a preset writing time.