Patents Examined by Thuan Du
  • Method and system for configuring a computer system via a wireless communication link
    Patent number: 7149884
    Abstract: A computing product is first assembled according to a predetermined hardware configuration and placed in a shipping container thus providing a containerized computer system. The computing product has a wireless communication subsystem for wirelessly receiving configuration information. The containerized computer system is fully configured before shipping the computer system to a predetermined customer by exchanging information between the wireless communication subsystem and a wireless information network in the manufacturing facility.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: December 12, 2006
    Assignee: Dell Products L.P.
    Inventors: Clint H. O'Connor, Damon W. Broder, Reynold L. Liao
  • Method and apparatus for enhancing the speed of a synchronous bus
    Patent number: 7143304
    Abstract: An apparatus for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk is supplied by the same PLL that provides the main clock signal lg_clk. According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: November 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Sharath Raghava, Kevin Normoyle, Christopher Furman
  • Automated power management system for a network of computers
    Patent number: 7143300
    Abstract: A computer system comprising a plurality of computing entities includes automatic power management logic that automatically transitions the system to a state in which less power is consumed when appropriate. The determination as to when this transition should occur is based on determining when demand for the processing abilities of the system are reduced. Once the decision has been made to transition to a reduced power state, the system's power management logic makes this transition in such a way to preferably minimize or at least reduce the performance impact on the system. Also, rather than altering the power state of one of the computing entities in the system, the entity can be deployed as part of another computing system.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: November 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark R. Potter, Thomas L. Buske, John M. Cagle, John M. Hemphill
  • Power saving in FPU with gated power based on opcodes and data
    Patent number: 7137021
    Abstract: A method and an apparatus are provided for saving power in a microprocessor. The microprocessor has at least one functional unit, which has a plurality of blocks. The blocks each include a plurality of sub-blocks. It is determined whether there is any instruction for the functional unit. Upon a determination that there is no instruction for the functional unit, the functional unit is shut down. Upon a determination that there is at least one instruction for the functional unit, at least one inactive block of the functional unit is shut down based on the instruction.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
  • Communication clocking conversion techniques
    Patent number: 7134038
    Abstract: A plurality of groups of first flip-flops (group 40 of flip-flops A1–An?1 for each of channels CIA–CIC) store input data clocked in response to first clock signals (A–C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of flip-flops B1–Bn for each of channels CIA–CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group 80 for each of channels CIA–CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: November 7, 2006
    Assignee: Broadcom Corporation
    Inventor: Wee Mon Wong
  • Clock synchronization apparatus and method of devices with different clocks
    Patent number: 7134033
    Abstract: A clock-synchronizing apparatus and method of devices with different clocks are disclosed. Between a first device operated with a first clock and a second device operated with a second clock faster than the first clock, an operation latency of the second device refers to the first clock, control signals that controls the second device are generated at the second clock speed according to the operation latency, and an enable interval of the control signals has a 1/4 clock period of the first clock. Accordingly, since the first device and the second device can transmit and receive a data to and from each other while being operated by using their own clock, an access latency for the first device to access the second device can be reduced and a transmission band width between the two devices can be effectively used.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: November 7, 2006
    Assignee: LG Electronics Inc.
    Inventor: Young-Suck Kim
  • Method of managing power of control box
    Patent number: 7131019
    Abstract: The present invention is to provide a method of managing power of a control box which, when powered on, causes a control module to perform the steps of running a power on management procedure to set a power on mode of each of a plurality of blade servers installed in the control box; measuring power consumed by the blade servers running in the power on mode; measuring power of a power supply; running a power consumption estimation procedure to determine whether the power of the power supply is larger than the power consumed by the blade servers, and determining whether a subsequent action should be continued by the control module based on the estimation.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: October 31, 2006
    Assignee: Inventec Corporation
    Inventor: Chun Liang Lee
  • Disk array device and method of supplying power to disk array device
    Patent number: 7131014
    Abstract: A disk array device and a method of supplying power to a disk array device to which power is supplied by at least two AC inputs are provided. Where at least two AC/DC power-supply groups are provided in correspondence with each of the AC inputs and each AC/DC power-supply group includes at least two AC/DC power supplies that are connected to the AC input corresponding to that group, outputs from the AC/DC power supplies are summed separately for each group to obtain group total outputs for each group, and the group total outputs are input to each of a plurality of loads in the disk array device to provide power to each of the loads.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: October 31, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Suzuki, Hiromi Matsushige, Masato Ogawa, Tomokazu Yokoyama
  • Requirements for supplying power to a device
    Patent number: 7127623
    Abstract: Hardware assemblies, either embedded (100) or external (400), which use software (101 or 800) for processes (330 to 356) such as acquiring power-related values (342), principally by the use of a connector (132) that accesses a battery (134), in order for a processor (102) to calculate an optimized power signal (338), and then to configure an output (344) of a power supply (122) to deliver the power signal to a powered device (136).
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: October 24, 2006
    Inventor: Patrick Henry Potega
  • Host interface for direct connection of an optical drive to an IDE/ATA data bus
    Patent number: 7124216
    Abstract: A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: October 17, 2006
    Assignee: Zoran Corporation
    Inventors: Phil Verinsky, Michael Case
  • Host interface for direct connection of an optical driver to an IDE/ATA data bus
    Patent number: 7124217
    Abstract: A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an integrated drive electronics (IDE) data bus or an industry standard architecture (ISA) data bus is disclosed. A digital signal processor (DSP) interface to the drive electronics of the CD drive, a dynamic random access memory (DRAM) controller, an error correction code (ECC) data corrector, an error detection and correction (EDC) device employing cyclical redundancy checking techniques (EDC/CRC), and a host computer interface are described.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: October 17, 2006
    Assignee: Zoran Corporation
    Inventors: Phil Verinsky, Michael Case
  • Method and device for data transfer
    Patent number: 7120818
    Abstract: Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: October 10, 2006
    Assignee: Infineon Technologies AG
    Inventors: Stefan Dietrich, Peter Schrögmeier, Sabine Kieser, Christian Weis
  • Instruction-initiated power management method for a pipelined data processor
    Patent number: 7120810
    Abstract: An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: October 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • System for controlling operation of a processor based on information contained within instruction word
    Patent number: 7114089
    Abstract: An instruction word is used to transfer information about whether the instruction word pertains to mode setting of a functional block. Instruction words included in the program code are processed in at least a first decoding step and a second decoding step, wherein in the first decoding step, said information included in the instruction word is examined. On the basis of the examination, it is determined whether the mode of one or more functional blocks is to be set or whether the second decoding step is to be taken, in which the instruction word is decoded to be run by one or more of said functional blocks. The invention also relates to a processor and an electronic device, in which the method can be implemented. The invention further relates to a program, in which a program code is provided for implementing the method.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 26, 2006
    Assignee: Nokia Corporation
    Inventor: Aki Launiainen
  • Selective suspension of bus devices
    Patent number: 7103788
    Abstract: A method and system for asserting power control over one or more hardware devices connected via a bus. The invention includes a method and system for signaling and waiting to suspend a first device connected to a second device. The invention also includes a method and system for suspending a tree of devices with one or more of the devices hierarchically organized as parent devices and child devices in the tree. A controller at a root of the tree receives an idle request from one or more of the child devices and suspends all devices in the tree after receiving an idle request from each of the child devices. The invention also includes an input/output control (IOCTL) data structure for communicating the idle request.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: September 5, 2006
    Assignee: Microsoft Corporation
    Inventors: Joseph G. Souza, Doron J. Holan, Kenneth D. Ray
  • Using a cache and data transfer methodology to control real-time process data in a PXE pre-boot manufacturing environment
    Patent number: 7103762
    Abstract: A method and system for caching and moving the required real-time, processing unit specific data (including boot image selection) among isolated servers in a pre-boot environment is disclosed. A system and method in accordance with the present invention provides a network/server topology that includes a common control server, and a plurality of isolated process servers. A system and method in accordance with the present invention provides the capability of being able to reference the real-time processing unit specific data based on either the unique processing unit identifier (MTSN directory name) or based on the MAC address (in conjunction with the content of a MAC binding file).
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: John Gary Harper, Barry Alan Kritt, Pamela Annette Morse, Linda Reed Newton, Paul Allen Roberts
  • System for identifying, based on setup use history, and displaying a setup of a system to indicate enabled and disabled setting items to a user
    Patent number: 7100030
    Abstract: A computer that can easily identify which setting items are enabled and which setting items are not enabled when conducting setup setting operations, and can efficiently conduct correct setup. Setup history information is stored when the use environment settings are executed in the computer, the user and/or others can identify and display in an easily recognizable state the setting items from among many setting items in which the setting values set during the setup setting operation are not reflected in the use environment of the computer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: August 29, 2006
    Assignee: Fujitsu Limited
    Inventors: Kenji Sakamaki, Masahiro Saito, Michisaburou Kihara, Kayo Mizutani
  • Protective relay with embedded web server
    Patent number: 7085938
    Abstract: A protective relay having an embedded web server to allow communication with a remote device having a standard web browser package. The relay can receive and transmit HTML files according to the HTTP protocol over a communications network. The relay can receive commands from the remote device, and can generate and return requested data to the remote device.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: August 1, 2006
    Assignee: General Electric Company
    Inventors: Marzio Pozzuoli, Norris Woodruff, Andrew Baigent, Scott Gilbertson
  • User interface for dynamic computing environment using allocateable resources
    Patent number: 7082521
    Abstract: The present invention discloses user interface for creating a dynamic computing environment using allocateable resources. The interface enables the fast, efficient selection and configuration of processing resources for the computing environment. The resources are fully selectable and allocable by a system architect. In a first embodiment, a primary company, Design2Deploy, Inc.® provides the ability for a customer or system architect to design a system by allocating resources and specifying how the resources are to be used. The system architect may create a computing environment from a remotely-accessible user interface such as a web page on the Internet. Thus, the system architect can create, modify and operate the environment from anywhere in the world.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: July 25, 2006
    Assignee: VERITAS Operating Corporation
    Inventor: Sekaran Nanja
  • Instruction dependent clock scheme
    Patent number: RE39252
    Abstract: A method and apparatus including a first circuit configured to receive multiple instructions including a first instruction having a first execution time, and to generate a first signal having a state dependent on the first execution time; a second circuit configured to receive the first signal and to generate a clock signal including a clock cycle having a period dependent on the state of the first signal; and a third circuit configured to receive the clock signal and execute a portion of the first instruction during the clock cycle, the first execution time corresponding to the portion of the first instruction.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventor: Vishram P. Dalvi