Abstract: In a network device, a connector module comprises a network connector coupled to the connector module in a configuration that transfers power and communication signals and an application connector that comprises serial media independent interface (SMII) pins and power pins. A Power-over-Ethernet (PoE) circuit is coupled between the network connector and the application connector.

Abstract: Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

Abstract: A boot method an apparatus are described which reduce the likelihood of a security breach in a mobile device, preferably in a situation where a reset has been initiated. A predetermined security value, or password, is stored, for example in BootROM. A value of a security location within FLASH memory is read and the two values are compared. Polling of the serial port is selectively performed, depending on the result of such comparison. In a presently preferred embodiment, if the value in the security location matches the predetermined security value, then polling of the serial port is not performed. This reduces potential security breaches caused in conventional arrangements where code may be downloaded from the serial port and executed, which allows anyone to access and upload programs and data in the FLASH memory, including confidential and proprietary information.

Abstract: Systems and methods for reducing problems and disadvantages associate with remotely booting multiple information handling systems are disclosed. A method may include obtaining system-specific parameters regarding a system including a plurality of remotely-booted clients, the system-specific parameters including a average client boot time threshold. The method may also include generating a plurality of client boot threads based on at least one or more of the system-specific parameters. The method may additionally include measuring an actual average client boot time of the plurality of client boot threads. The method may further include determining a number of remotely-booted clients for substantially simultaneous remote booting based on at least the actual average client boot time and the average client boot time threshold.

Abstract: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

Abstract: In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If data communication over the bus is addressed to the device then the selective portion of the device, including the device clock, is triggered to return to a power on state from the power off state. The data communication is stored in shadow registers using a bus clock while the device clock is transitioning to the power on state. The data communication stored in the shadow registers is transferred to a register map under the control of the device clock operating in the power on state. Upon completion of the transfer of the data communication to the register map, the device is returned to operate in the power saving mode.

Abstract: Provided are a method and apparatus for managing power of a portable information device. The apparatus includes: a display unit displaying a power management mode picture when a wake-up signal is input during a low-power consumption state of the portable information device; and a processing unit setting the portable information device again in the low-power consumption state when a user's input, as a response to the power management mode picture, is not received within a predetermined time after the power management mode picture is output to the display unit. Accordingly, even when a button on the portable information device is accidentally pressed, battery thereof can be prevented from being needlessly consumed.

Abstract: A system and method for secure communication for power over Ethernet (PoE) between a computing device and a switch. Various power management information can be used as inputs in a process for determining a power request/priority. This power management information can be communicated in Layer 2, Layer 3, or higher messaging during initial power allocation and ongoing power reallocation. Encryption of such messaging enables confidentiality, secure allocation processes, and prevention of denial of service attacks.

Abstract: Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or extended over multiple clock periods. Automated clock relationship detection between two clocks may comprise (a) a shift register synchronizer that reduces the possibility of metastability while capturing and temporarily storing samples of the first clock in response to cycles of the second clock and (b) an evaluator that processes the samples to determine the relationship. A clock relationship detector may also determine the relationship of two clocks by arbitrating a plurality of preliminary determinations of the relationship. Delays may be applied so that each of several detectors receives a clock at a different time, which may avoid metastability in the majority of detectors. The relationship may be used to reliably determine an operating mode of logic driven by one of the clocks.

Abstract: In an integrated circuit (IC) may have several functional blocks adapted to be inactivated independently from each other. At least one firewall cell may be embedded independently of other firewall cells in the vicinity of one functional block. The firewall cell may be electrically isolated from the functional block and may be powered by a constantly supplied voltage source in the IC. Firewall cells may be embedded in free locations on the IC in the functional block domain according to a design that may be free of constraints such as firewall cells array of firewall cells mini-island.

Abstract: A method including monitoring whether an externally originating signal reaches a predetermined threshold value in a host, producing an output value based on the monitoring, and identifying a power environment for the host based on the output value is described. Also described is a method for determining the power environment of a host. Systems and hosts for implementing the methods are also described.

Abstract: In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a boot block stored at a first memory location, a capsule update stored at a second memory location, a startup authenticated code module to ensure the integrity of the boot block upon a restart of the processor-based system, code which is executable by the processor-based system to cause the processor-based system to validate the boot block with the startup authenticated code module upon the restart of the processor-based system, and, if the boot block is successfully validated, to validate the capsule update for the processor-based system with the startup authenticated code module. Other embodiments are disclosed and claimed.

Abstract: A solid state disk (SSD) device includes a non-volatile storage module (NVSM), a secondary power source coupled to power inputs of the SSD, a volatile memory (VM), a controller in communication with the NVSM and the VM. The controller is operable in a (re)populate mode to (re)populate data stored in the NVSM to the VM when primary power is initially applied to power inputs of the SSD and further operable in a primary power on mode to replicate data to the NVSM that was written to the VM in response to received I/O requests while primary power is applied to the power inputs of the SSD. The secondary power source can be decoupled from the power inputs of the SSD while the controller is operating in either the (re)populate mode or the primary power on mode.

Abstract: A method of using BIOS information can include exporting first BIOS information from a first information handling system. The method can further include initiating a boot sequence for the second information handling system and importing second BIOS information into a second information handling system after initiating the boot sequence and before initiating an operating system, wherein the second BIOS information is associated with the first BIOS information. The method can further include initiating an operating system of the second information handling system after importing the second BIOS information. The first and second BIOS information may be the same, or the second BIOS information may be derived from the first BIOS information. The first and second information handling systems may be the same or different. In one embodiment, the first BIOS information can be translated into a text file for editing before using the second BIOS information during a boot sequence.

Abstract: Embodiments of the invention provide systems and methods associated with a measurement engine in a server platform. In one such embodiment of the invention, the measurement engine hardware verifies/authenticates its own firmware and then system initialization firmware by measuring such firmware and storing measurement results in a register that is not spoofable by malicious code. In this instance, the measurement engine holds the host CPU complex in a reset state until the measurement engine has verified the system initialization firmware. In another such embodiment of the invention, the measurement engine hardware also measures firmware associated with one or more system service processors and stores such measurement results in a register. In this case, the measurement engine holds the system service processors and the host CPU complex in reset until the measurements are completed. Other embodiments are described.

Abstract: A mode-switching system, comprising plural switches, a timer, and a controller, is provided. The mode-switching system switches an operation mode of a first unit to one of normal and power-saving modes. The plural switches separately correspond to plural specific functions. Each of the specific functions is carried out when the corresponding switch is switched on. The timer clocks the elapsed time since the switching operation is carried out for any of the switches. The controller switches the operation mode to the power-saving mode from the normal mode when the elapsed time exceeds a threshold value determined for the switch for which the latest switching operation has been carried out. The threshold value is determined individually for each of the switches.

Abstract: A power management unit (PMU) may promote a processing core from a working state to a first non-working power saving state after receiving a signal from an automatic core C-state promotion (ACCP) unit. An OS component may detect the idling of the processing core and may initiate the ACCP. The ACCP may initiate the PMU to promote the processing core to a first non-working power saving state. The ACCP may track the residency time of the processing core in the first non-working power saving state and may initiate the PMU to promote the processing core to a next non-working power saving state if residency time of the processing core in the first non-working power saving state exceeds a first value. The ACCP may initiate the PMU to demote the processing core back to the working state if a break event occurs during the residency time.

Abstract: A mobile electronic communication device power management method and apparatus are disclosed for use in multiple processor hardware schemes having asymmetrical power demands between processors. Upon reaching an long duration idle state, a high-level processor with high power consumption requirements handling low-level system tasks updates a data set shared between processor subsystems containing information necessary to perform such low-level tasks. A proxy software module is initiated on a base-band processor with lower power consumption requirements. The proxy module accesses the shared data set and begins to control low-level system tasks, allowing the high-level processor to enter a dormant low power state. Upon the occurrence of a wake-up event, the high-level processor enters an active state. The shared data set is updated by the proxy software module and the proxy module is terminated. The high-level processor accesses the shared data set and resumes control of low-level system tasks.

Abstract: A power tool system component has a microprocessor, a one wire communication terminal connecting the microprocessor to an external device, and a flash memory storing: (a) an application program governing operation of an application mode during which the power tool system component is operated; and (b) a boot loader program governing operation of a boot loader mode during which at least part of the application program can be updated. The microprocessor accesses the flash memory and implements the boot loader program and the application program by setting up and observing a temporal window during which one or more predetermined conditions must be met for the boot loader mode to be entered. The predetermined conditions include successful completion of a calibration process that includes sending a calibration byte to the external device according to a format predetermined to allow the external device to adjust its baud rate for sending and receiving information.

Abstract: According to one embodiment, an information processing apparatus includes: an information processing apparatus main body receiving a supply of power from power supplies disposed at outside or inside; one or a plurality of connection connector(s) constituted to be able to attach/detach an external apparatus, and having at least one signal terminal transmitting/receiving signals between the information processing apparatus main body and the external apparatus and at least one power terminal supplying the power from the power supplies to the external apparatus; a power supply state changing portion having a switch provided between the power supply and the power terminal, and capable of changing the switch to either one of a connection state or a non-connection state; and a power supply state control portion having user setting information set by a user concerning a control method of the power supply state changing portion, and performing a control to change the switch to either one of the connection state or the