Abstract: A method and system are provided for dynamically managing delivery of power to partitionable elements in a computer system while supporting terms of a Service Level Agreement (SLA). Parameters of the SLA are gathered in conjunction with the topology of the computer system. Transactions associated with the SLA are monitored and high and low usage periods are predicted based upon a history of transactions. Power to partitionable elements of the computer system may be adjusted during high and low usage periods. In addition, dynamic management of the partitionable elements is provided in response to current demands. Management of the partitionable elements is all made in compliance with the SLA.

Abstract: A memory system including independent power for each memory module. The memory system includes a plurality of memory modules each including a plurality of memory chips configured to store data. The memory system further includes a power conversion unit coupled to provide power to each of the plurality of memory modules via a respective power conduit. Each of the respective power conduits is electrically isolated from each other power conduit.

Abstract: A sub-system may maintain the network connectivity of the device, while the device is operating in low power. The sub-system may determine whether a pre-specified pattern is present in the incoming packet. The sub-system may send network messages such as keep-alive or time-out messages on behalf of the device if a first pattern is detected in the incoming packet. A first action associated with the first pattern may indicate that a network message is to be sent to another device. The sub-system may send a wake-up signal to the device if a second pattern is detected in the incoming packet. A second action associated with the second pattern may indicate that a wake-up signal is to be sent to the device.

Abstract: In some embodiments, the invention involves a system and method to provide maximal boot-time parallelism for future multi-core, multi-node, and many-core systems. In an embodiment, the security (SEC), pre-EFI initialization (PEI), and then driver execution environment (DXE) phases are executed in parallel on multiple compute nodes (sockets) of a platform. Once the SEC/PEI/DXE phases are executed on all compute nodes having a processor, the boot device select (BDS) phase completes the boot by merging or partitioning the compute nodes based on a platform policy. Partitioned compute nodes each run their own instance of EFI. A common memory map may be generated prior to operating system (OS) launch when compute nodes are to be merged. Other embodiments are described and claimed.

Abstract: A system for minimizing power consumption of a multiprocessor data storage system is disclosed. The system utilizes processors that are capable of operating at a number of different reduced power modes, such that the processors operate at full power during peak workloads, but can be powered down during low workload times. When the onset of peak loads are detected through monitoring I/Os per second (“IOPS”) and/or response times of the system, the processors are brought out of power-down mode to handle the increased IOPS during the peak loads. In this manner, the majority of the processors only operate at full power when the system experiences peak loads. During normal and low load times, the processors are either operated at reduced power or are powered down. This results in a significant reduction in power consumption of the system.

Abstract: A system delivers power to a powered device through a local area network using a power sourcing equipment to process data of an interconnected network and to receive power from a first power source coupled to the power sourcing equipment. The system may include a powered device coupled at a distance away from the power sourcing equipment through a local area network (LAN) to process the data of the interconnected network through the power sourcing equipment. The powered device may include a modular power over LAN circuit to enable power to the powered device through the LAN when the modular power over LAN circuit is coupled to the powered device.

Abstract: In a network device, a connector module comprises a network connector coupled to the connector module in a configuration that transfers power and communication signals and an application connector that comprises serial media independent interface (SMII) pins and power pins. A Power-over-Ethernet (PoE) circuit is coupled between the network connector and the application connector.

Abstract: System configuration data is transferred from a master integrated circuit to a shadow integrated circuit in a computer system before the system is initialized. The configuration data is initially stored in configuration registers in the master integrated circuit. The configuration data may include values that are programmed via hardware (e.g., strapped pin values) or software (e.g., default or overridden values). A CPU accesses the configuration data in the configuration registers through a host module of the shadow integrated circuit. A copy of the configuration data is transferred to shadow registers in the shadow integrated circuit. After system initialization, the CPU may execute software to read configuration values directly from the configuration registers on the master integrated circuit. The CPU may also execute a write operation on the configuration data in both the configuration registers and the shadow registers such that the configuration settings are consistent across the system.

Abstract: A method and system for power management including device controller-based device use evaluation and power-state control provides improved performance in a power-managed processing system. Per-device usage information is measured and evaluated during process execution and is retrieved from the device controller upon a context switch, so that upon reactivation of the process, the previous usage evaluation state can be restored. The device controller can then provide for per-process control of attached device power management states without intervention by the processor and without losing the historical evaluation state when a process is switched out. The device controller can control power-saving states of connected devices in conformity with the usage evaluation without processor intervention and across multiple process execution slices. The device controller may be a memory controller and the controlled devices memory modules or banks within modules if individual banks can be power-managed.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: Embodiments of the present invention provide a method and apparatus for managing power states in a personal computing device, while maintaining a perception by the user of “instant on” functionality. In various embodiments of the invention, the power states are presented to the user as a simple on/off option and the power management protocol is not visible within the user interface of the personal computing device thereby providing the user with the impression that the system is operating with a simple binary on/off protocol.

Abstract: A print engine comprising at least one print controller and at least one associated authentication device is provided. Each authentication device has a processor, non-volatile memory, an input for receiving power from a power supply and a power detection unit. Each authentication device is configured to enable multi-word writes to the non-volatile memory under control of the associated print controller. The processor is configured to control and trim the amount of power supplied to the input to predetermine a threshold at which operation of the authentication device is established. The power detection unit is configured to monitor a voltage level of the power supplied to the input, and in the event the voltage level drops below the predetermined threshold, preventing subsequent words in any multi-word write currently being performed from being written to the memory.

Abstract: In a serial communication system in which data is transmitted from a first unit to a second unit in synchronization with a clock signal, the mode of communication between the first and second units is switched between a first communication mode in which data is transmitted from the second unit to the first unit in synchronization with the clock signal, and a second communication mode in which a signal asynchronous to the clock signal is transmitted from the first unit to the second unit.

Abstract: A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part.

Abstract: In one embodiment, the present invention includes a method for receiving an information packet in a first port from an interconnect while an agent associated with the first port is in an idle low power state, transmitting a first signal from the first port along the interconnect to request re-transmission of the information packet, and sending a second signal from the first port to the agent to cause the agent to enter a fully active power state. Other embodiments are described and claimed.

Abstract: According to a method of data processing in a data processing system, a hardware management component receives from a software component of the data processing system a request for management access to a hardware component of the data processing system. In response to receipt of the request for management access, the hardware management component determines whether or not the request contains a parameter indicative of the intended scope of hardware components to be accessed in response to the request. In response to the request, the hardware management component selects a scope in accordance with the determination and issues one or more hardware management commands to one or more target hardware components of the data processing system within the selected scope, such that an operating state of the one or more target hardware components is modified.

Abstract: In one embodiment, the present invention includes a counter to count core clocks, where the counter has a value to be incremented from zero to one less than a first bus ratio. Coupled to the counter may be a control logic to generate a control signal to change from the first bus ratio to a second bus ratio, where the control logic is coupled to receive the counter value and control the counter based on this value. In this way, the bus ratio can change without draining the transaction queues of a processor. Other embodiments are described and claimed.

Abstract: A method for generating a wide range of clock rates from a single clock. A delta is generated from a first clock signal and a second clock signal. An accumulative offset is generated from adding the delta to a previous accumulative offset for each clock period of the first clock signal. Whenever an overflow is encountered, the value of the accumulative offset is truncated. The second clock signal is interpolated between adjacent values.

Abstract: Battery information is transmitted from a recording and playback apparatus to a host computer. In the host computer, based on the time for which the operation can be continued, corresponding to the current operating status and the remaining battery level, stored in the battery information, a warning is output, the data of a cache memory is written, data writing prohibition is set, and a forced closing process is performed. With this construction, in a system formed of a recording and playback apparatus, such as a CD-R/RW drive unit, and a personal computer, a proper system operation corresponding to the remaining battery level of the recording and playback apparatus is obtained, and the data recorded on the recording medium is prevented from being destroyed as a result of operation stopping due to, for example, the remaining battery level becoming zero.

Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.