Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.

Abstract: Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Abstract: A computer includes an extensible firmware interface with a storage device enumeration function that performs storage device enumeration operations in parallel.

Abstract: Embodiments disclosed herein describe a network interface device including a first powered device controller coupled to first and second power supply lines. A second powered device controller coupled to third and fourth input power supply lines. A dc-dc converter coupled to receive a single signal representing a sum of power signals output by the first and second powered device controllers.

Abstract: Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.

Abstract: A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

Abstract: When booting a host, a host peripheral system sends a boot code to the host for controlling the booting operation of the host via a serial transmission line, and loads an external program code into the host. After setting up a transmission mechanism through executing the external program code, the host can forward a write command to the host peripheral system for writing the data provided by the external program code to the command identification sector of the non-volatile memory of the host peripheral system, and the host peripheral system is capable of identifying the data as a command and executes functional operations corresponding to the command. After finishing the functional operations, the host peripheral system forwards a finish signal to the host, and the host is able to send a read command for fetching the data signal generated in the functional operations.

Abstract: A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.

Abstract: A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.

Abstract: An apparatus for providing management storage via a USB port of a computer system is disclosed. The apparatus includes a flash memory, a first and second switches, a first and second inverters, a designated port, and a controller. Coupled to the flash memory, the first and second switches are controlled by a main power of a computer system in a complementary manner. The first and second inverters, which are powered by a standby power of the computer system, are coupled to a respective control input of the first and second switches. The designated port, which is coupled to the flash memory via the first switch, allows data to be read from and written to the flash memory without booting up the computer system. On the other hand, the controller, which is coupled to the flash memory via the second switch, allows data to be read from and written to the flash memory by the computer system only after the computer system has been booted up.

Abstract: A pipelined computer system with power management control in accordance with one or both of a power management signal and a power management instruction.

Abstract: A disk drive is disclosed wherein during a first boot operation, first boot data is transmitted from a first plurality of data sectors to a host, and a first log identifying the first plurality of data sectors is maintained. During a second boot operation, second boot data is transmitted from a second plurality of data sectors to the host, and a second log identifying the second plurality of data sectors is maintained. During a third boot operation, data sectors identified by the first and/or second logs are pre-fetched into a cache.

Abstract: The conventional techniques cannot set optimal energy saving modes separately for a plurality of loads and can hardly attain further suppression of power consumption. To accomplish this, in an image forming apparatus including a main circuit board which has a master CPU and controls the operation of the entire image forming apparatus, and a plurality of sub circuit boards each have a slave CPU and control each corresponding control target, the operating condition of each slave CPU is stored in correspondence with the operation mode of the image forming apparatus, and, upon being notified of the operation modes of the image forming apparatus, the slave CPU of each of the plurality of sub circuit boards sets the operation status of the slave CPU by referring to the table of the operation modes.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: This invention provides a remote control capable of automatically sending signals to a variety of electronic devices so that a user does not have to send signals to each of the electronic devices individually. The remote control may include a dedicated button that when activated may send signals to a plurality of electronic devices to perform one or more operations. The remote control may send the signals simultaneously or sequentially. The signals may be also encoded with the specific address for each of the plurality of electronic devices. This way, only the electronic device with the matching address may receive the signal. The signals may be also encoded with any number of commands such as turn “on” or turn “off” so that each electronic device may perform a similar or different operation as other electronic devices. The remote control may be any type of device that may be distinct from the electronic device such as a hand-held device.

Abstract: Methods, apparatus, and products for selecting a redundant power supply mode for powering a computer system are disclosed that include detecting, by a voltage monitoring module, an input voltage level of a power supply; determining, by the voltage monitoring module, whether the input voltage level of the power supply is greater than a predetermined threshold value; if the input voltage level of the power supply is greater than the predetermined threshold value, configuring, by the voltage monitoring module, the power supply for an N+N redundant power supply mode having N primary power supplies and N redundant power supplies; and if the input voltage level of the power supply is not greater than the predetermined threshold value, configuring, by the voltage monitoring module, the power supply for an N+M redundant power supply mode having N primary power supplies and M redundant power supplies, where N is greater than M.

Abstract: When power to a storage device is turned on and the storage device can accept a data input and output request being transmitted from an information processing device, the storage device transmits a power-on request for turning on power to the information processing device. The storage device, when it accepts a stop-power instruction, transmits a stop-power request for stopping power to the information processing device.

Abstract: A circuit is attached in parallel to a universal serial bus interface of a data processing system. A capacitor in the circuit is charged by receiving power from a power pin of the universal serial bus interface while the data processing system is not in a reduced power state. A vibration sensor is unpowered while the data processing system is not in a reduced power state. The vibration sensor is disconnected from a data pin of the universal serial bus interface while the data processing system is not in a reduced power state. When the data processing system enters a reduced power state, the capacitor provides power to the vibration sensor. When a vibration is detected by the vibration sensor, a switch connects the vibration sensor to the data pin of the universal serial bus interface, providing a wake up signal to the data processing system.

Abstract: An improved method and apparatus manages communications port contention and power consumption for a handheld computer, particularly handheld computers with a communications protocol that boosts power consumption when active, such as an RS-232 protocol. The improved method provides communications channel management that automatically opens the communications channel in response to a wake-up signal sent to a handheld computer from a peripheral device. The computer peripheral device is explicitly and/or implicitly identified. The opened communications channel is closed in response to receiving some data from the peripheral device, and/or after a device timeout expires without the handheld computer receiving data from the computer peripheral device.