Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.

Abstract: A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.

Abstract: A method and apparatus for securely updating and booting a code image is provided, where a code image is updated in a storage medium storing an operating system having a first region, on which a boot code is loaded, a second region, in which a first code image is stored, and a third region, in which the boot code and first check data for verifying the first code image are stored. Updating a code image includes storing a second code image in the second region, extracting information about a secure one-way function from the first check data, and generating second check data for verifying the second code image using the extracted information of the secure one-way function and storing the generated second check data in the third region. When the second check data is set as a parameter of the secure one-way function, the first check data is generated.

Abstract: A peripheral device has a bus-controlled switching arrangement for operating a power supply. A device comprises a bus interface adapted for communicating with a remote device via a bus. A switch circuit is connected between the bus interface and a power supply. The switch circuit is operative, when the power supply is in an inactive state, for sensing bus activity and for generating a signal for activating the power supply in response to the sensed bus activity, wherein the switch circuit has no power dissipation when no activity is sensed on the bus.

Abstract: One embodiment disclosed relates to a system for power management of a group of computers. The system includes server side infrastructure (SSI) circuitry at each computer in the group and a centralized power management module (CPMM). The SSI circuitry includes local monitoring circuitry coupled to a central processing unit (CPU) of the computer. The CPMM has a management link to the SSI circuitry at each computer in the group. The local circuitry at each computer monitors power consumption at the CPU of that computer and transmits power consumption data to the CPMM. The CPMM applies a set of rules to the power consumption data to determine when and at which computers to enable and disable a CPU power throttling mode.

Abstract: A switching mode power supply includes a transformer which includes a primary winding and two secondary windings. One secondary winding and the primary winding constitute a forward circuit. The other secondary winding and the primary winding constitute a flyback circuit. The switching mode power supply also includes a power storing circuit and an output terminal. The power storing circuit is interposed between the forward circuit, the flyback circuit, and the output terminal.

Abstract: The present invention relates to an apparatus and a method for managing power in a computer system. A filter driver can be equipped with a packet monitoring function or the like detects whether devices mounted in the computer system are in the idle state. If a device is in the idle state, the power mode of the corresponding device is varied to the power down mode, independent of the system power mode state that has been set up by the operation system in the computer system. In this manner, power supplied to devices in the idle state is reduced, and it becomes possible to have a more efficient control over the load of the computer system. Overall, preferred embodiments according to the present invention can be very advantageously used for developing and expanding the computer system more simply by adding the filter driver into the system, without changing a device driver in the computer system.

Abstract: A system enabling computing to be provided as a packaged product or as a remote resource to users. Computing is delivered as a product or a resource by providing dynamic computing environments to users based on users' choices of virtual components (hardware, software or network components). A customer can choose the components and configure a computing environment. The system packages this environment and makes it available for users to compute. A service provider can use the system to create computing environments, automatically, on demand and thus providing computing as a remote resource to customers. The system monitors the usage of the customers and they are billed accordingly. In either case users can carry out their computing activity remotely using a client device such as a web browser.

Abstract: A multiprocessor power-on switch circuit applied to a mainboard having multiple power-on circuits is provided, in which each power-on circuit includes a peripheral circuit corresponding to a processor. A selection circuit in the power-on switch circuit is responsible for selecting a power-on circuit as a first power-on circuit or a second power-on circuit. When the mainboard is powered on, a detection circuit in the power-on switch circuit receives a status signal from the first power-on circuit performing the power-on action. When the status signal is determined as a fault signal by the detection circuit, a control signal is output to the selection circuit, so as to make the selection circuit set the second power-on circuit as the power-on circuit to actuate the mainboard.

Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.

Abstract: A system for managing network alerts including data connections adapted to receive alerts from network sensors, alert processing logic coupled to the data connections and further including alert integration logic operable to integrate the alerts, report generation logic coupled to the alert integration logic, distribution logic coupled to the report generation logic and a remote management unit coupled to the alert processing logic and being operable to dynamically modify the alert processing logic.

Abstract: A computer system comprising a processor, a first storage coupled to the processor and comprising an operating system, and a second storage coupled to the processor. The processor is adapted to store a group of files pertaining to the operating system on the second storage prior to launching the operating system. The processor is capable of using the group of files to restore the operating system.

Abstract: A system for generating and monitoring voltages on a variety of different components on a common printed circuit board. The system includes a programmable controller, a plurality of DC/DC converters for producing voltages for the devices and a plurality of voltage regulators for produced voltages for a plurality of CPUs on the board, such CPU voltages being produced in accordance with VIDs provided to the regulator by the CPU. The programmable controller: establishes a set point voltage for such one of the DC/DC converters; sequentially monitors the produced voltages produced, monitors voltages produced by the regulators for the CPUs by comparing the VIDs to the voltages produced by the regulators, and if during the sequencing any one of the converters is determined by the programmable controller as producing an improper voltage or if the any one of the regulators fails top produce the voltage indicated by the VIDs, disables the board.

Abstract: A method and apparatus for virtualized and adaptive configuration. An embodiment of a method includes generating a system configuration. The configuration includes a setting, with the setting having an abstract value to be resolved based at least in part on a characteristic of a system. The configuration is installed in a recipient system, and a value is resolved for the setting based at least in part on a characteristic of the recipient system.

Abstract: A clock supplying apparatus capable of suppressing a current fluctuation as much as possible when supply of a clock signal to a circuit block is started or stopped. At start or termination of the clock signal supply to the circuit block, the clock signal frequency is temporarily changed to a low frequency lower than a standard frequency.

Abstract: A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Abstract: Disclosed is a synchronous semiconductor device including clock generation circuit that frequency divides a clock signal (PCLK) input from an input buffer and generates first and second internal clock signals having a predetermined phase difference from first and second frequency-divided clock signals of different phases, respectively, a first input circuit control unit that receives a chip select signal and samples the chip select signal in synchronization with the clock signal, second and third input circuit control units that sample an output of the first input circuit control unit in synchronization with the first and second internal clock signals, respectively, and first and second input circuits that receive a result of a logic operation between the output of the first input control unit and an output of the second input circuit control unit and a result of a logic operation between the output of the first input circuit control unit and an output of the third input circuit control unit as input enable s

Abstract: A disk array device and a method of supplying power to a disk array device to which power is supplied by at least two AC inputs are provided. Where at least two AC/DC power-supply groups are provided in correspondence with each of the AC inputs and each AC/DC power-supply group includes at least two AC/DC power supplies that are connected to the AC input corresponding to that group, outputs from the AC/DC power supplies are summed separately for each group to obtain group total outputs for each group, and the group total outputs are input to each of a plurality of loads in the disk array device to provide power to each of the loads.

Abstract: A system and method of power management for computer processor systems, the method including measuring power usage; monitoring execution of instructions for a finishing instruction; determining a finishing instruction address for the finishing instruction; determining measured power usage for the finishing instruction; and storing the finishing instruction address in association with the measured power usage in a Power History Table (PHT). The information stored in the PHT can be employed to manage the power used by the computer processor system.

Abstract: An information processing terminal includes a WOL monitoring unit for monitoring whether or not a particular packet for indicating resumption of operation from a suspended state is received, a resume processing unit for resuming the operation from the suspended state, a factor monitoring unit for recording a factor of the resumption to a memory, a cancel monitoring unit for monitoring whether or not a cancel signal to a communication request received after the resumption is received, and a suspend processing unit for switching the operation to the suspended state when the factor of the resumption is reception of the particular packet as well as the cancel signal is received after the resumption. With this arrangement, power consumption of the information processing terminal can be suppressed.