Abstract: A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.

Abstract: Provided on a chip are a plurality of conductor patterns for forming a coil, and a connection-relationship control device for controlling connection between adjacent conductor patterns. By switching the connection relationship of the conductor patterns by the connection-relationship control device, it is possible to form a coil of a desired shape at a desired position.

Abstract: A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE. Various alternative methods are disclosed.

Abstract: In one embodiment, a shift register memory includes a substrate, and a channel layer provided on the substrate, and having a helical shape rotating around an axis which is perpendicular to a surface of the substrate. The memory further includes at least three control electrodes provided on the substrate, extending in a direction parallel to the axis, and to be used to transfer charges in the channel layer.

Abstract: It is an object to provide a nonvolatile semiconductor storage device that prevents increase in a contact resistance value due to etching of a semiconductor layer when etching an interlayer insulating film and that has superiority in a writing characteristic and an electric charge-holding characteristic, and a manufacturing method thereof. A conductive layer is provided between a source or drain region and a source or drain wiring. The conductive layer is made of the same conductive layer that forms a control gate electrode. An insulating film is provided so as to cover the conductive layer, and the insulating film has a contact hole for exposing part of the conductive layer. The source or drain wiring is formed so that the contact hole is filled.

Abstract: A thermally conductive LED assembly is disclosed. The thermally conductive LED assembly includes an elongate conductor cable having a first conductor and a second conductor extending along a length of the elongate conductor cable and a thermally conducting and electrically insulating polymer layer disposed between first conductor and second conductor and a second electrically insulating polymer layer is disposed on the first conductor or second conductor. The electrically insulating polymer layer having a thermal impedance value in a range from 2.5 to 15 C.°-cm2/W and a plurality of light emitting diodes are disposed along the length of the elongate conductor cable. Each light emitting diode is in electrical communication with the first conductor and the second conductor.

Abstract: In a photodetector 1, a low-resistance Si substrate 3, an insulating layer 4, a high-resistance Si substrate 5, and an Si photodiode 20 construct a hermetically sealed package for an InGaAs photodiode 30 placed within a recess 6, while an electric passage part 8 of the low-resistance Si substrate 3 and a wiring film 15 achieve electric wiring for the Si photodiode 20 and InGaAs photodiode 30. While a p-type region 22 of the Si photodiode 20 is disposed in a part on the rear face 21b side of an Si substrate 21, a p-type region 32 of the InGaAs photodiode 30 is disposed in a part on the front face 31a side of an InGaAs substrate 31.

Abstract: A first cavity-down ball grid array (BGA) package includes a substrate member and an array of bond balls. The array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls. A surface-mount blocking element is disposed between the row of inner signal bond balls and the pair of rows of outer mesh bond balls. The surface-mount blocking element is either a passive or an active component of the BGA package. In one example, the first cavity-down BGA package is surface-mounted to a second cavity-down BGA package to form a package-on-package (POP) security module. The surface-mount blocking element provides additional physical barrier against the probing of the inner signal bond balls. Sensitive data is therefore protected from unauthorized access.

Abstract: An apparatus includes first and second microphone arrangements, arranged to output first and second signals respectively and is operable in a first mode and a second mode. In the first mode, an output signal is generated based on the second signal and a third signal, where the second signal and, optionally, the first signal, can be used to compensate for ambient noise, for example, for noise cancellation when a telephone call is relayed through a speaker. In the second mode, an output signal is generated based on the first and second signals. In this manner, the combination of the first and second microphone arrangements provides a directional sensitivity that can pick up sound from a remote source, for example, in an audio or video recording session. The apparatus may include a sensor to allow automatic switching between one or more of modes, directional sensitivity patterns and types of recording session.

Abstract: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.

Abstract: An integrated circuit package system includes: forming a first lead and a second lead; connecting an integrated circuit die with the first lead; forming an encapsulation over the integrated circuit die, the first lead, and the second lead with a portion of a top side of the second lead exposed; and forming a shield over the encapsulation, the first lead, and the second lead with the shield not in contact with the first lead.

Abstract: Trench-generated transistor structures, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of a semiconductor-on-insulator (SOI) wafer. The gate electrode may be defined from the semiconductor layer of the SOI wafer, which is separated from the handle wafer by an insulating layer. Alternatively, the gate electrode may be defined as a conventional gate stack on a shallow trench isolation region in the semiconductor layer or as a conventional gate stack in one of the BEOL interconnect levels.

Abstract: A semiconductor component includes a semiconductor chip, and a passive component, with the semiconductor component including a coil as the passive component. The semiconductor chip and the passive component are embedded in a plastic encapsulation compound with connection elements to external contacts.

Abstract: A nitride semiconductor free-standing substrate includes a nitride semiconductor crystal and an inversion domain with a density of not less than 10/cm2 and not more than 600/cm2 in a section parallel to a surface of the substrate and inside the substrate. A method for making the nitride semiconductor free-standing substrate includes a nitride semiconductor crystal growth step of growing on a heterosubstrate a nitride semiconductor crystal including an inversion domain with a density of not less than 10/cm2 and not more than 600/cm2 by adjusting a growth condition at an initial growth stage of the nitride semiconductor crystal, and a separation step for separating the grown nitride semiconductor crystal from the heterosubstrate to form the nitride semiconductor free-standing substrate.

Abstract: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially eliminates the possibility of the high-frequency analog signal transmitting to the control terminal pad. Accordingly, an increase in insertion loss can be suppressed.

Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.

Abstract: An imager device is disclosed including a first substrate having an array of photosensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.

Abstract: In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.

Abstract: Illumination assemblies, components, and related methods are described. An illumination assembly can include at least one solid state light-emitting device, an emission surface through which light is emitted, and a wavelength converting material that wavelength converts at least some light emitted by the solid state light-emitting device. The wavelength converting material can have a first density per unit area of the emission surface at a first location and a second density per unit area of the emission surface at a second location, wherein the second density is substantially different from the first density, and wherein the density per unit area is defined with a 1×1 cm2 averaging area. Another illumination assembly can include a light guide configured to receive light emitted by a solid state light-emitting device. The light guide can have a length along which received light propagates and an emission surface substantially parallel to the length of the light guide and through which light is emitted.

Abstract: A semiconductor composite apparatus, includes a first substrate, a semiconductor thin film layer, active devices, first driving circuits, and second driving circuits. The semiconductor thin film layer is formed on the first substrate and is formed of a first semiconductor material. The active devices are formed in the semiconductor thin film layer. The first driving circuits is formed of a second semiconductor material and performing a first function in which the active devices are driven. The second driving circuits are formed of a third semiconductor material and performing a second function in which the active devices are driven, the second function being different from the first function.