Abstract: A semiconductor component including a drift zone and a drift control zone. One embodiment provides a transistor component having a drift zone, a body zone, a source zone and a drain zone. The drift zone is arranged between the body zone and the drain zone. The body zone is arranged between the source zone and the drift zone.

Abstract: A novel MOS transistor structure and methods of making the same are provided. The structure includes a MOS transistor formed on a semiconductor substrate of a first conductivity type with a plug region of first conductivity type formed in the drain extension region of second conductivity type (in the case of a high voltage MOS transistor) or in the lightly doped drain (LDD) region of second conductivity type (in the case of a low voltage MOS transistor). Such structure leads to higher on-breakdown voltage. The inventive principle applies to MOS transistors formed on bulky semiconductor substrate and MOS transistors formed in silicon-on-insulator configuration.

Abstract: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (?m).

Abstract: Trench-generated transistor structures, methods for fabricating transistors using a trench defined in a semiconductor-on-insulator (SOI) wafer, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of the SOI wafer. The gate electrode may be defined from the semiconductor layer of the SOI wafer, which is separated from the handle wafer by an insulating layer. Alternatively, the gate electrode may be defined as a conventional gate stack on a shallow trench isolation region in the semiconductor layer or as a conventional gate stack in one of the BEOL interconnect levels.

Abstract: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.

Abstract: The display device according to an exemplary embodiment of the present invention includes an insulation substrate, a first signal line formed on the insulation substrate, a second signal line intersecting and insulated from the first signal line, an covering member formed on the second signal line, and a switching element having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the first signal line and the second terminal is connected to the second signal line, and a pixel electrode is connected to the third terminal of the switching element. The covering member according to an embodiment of the present invention reduces the etching error in forming a fine pattern.

Abstract: A solid-state imaging apparatus that performs color imaging using visible light and imaging using infrared light, the solid-state imaging apparatus including a plurality of two-dimensionally arranged pixel cells, in each of which a filter mainly transmits one of visible light and infrared light, wherein filters are arranged such that a first unit of arrangement where a plurality of filters that mainly transmit visible light are arranged and a second unit of arrangement where a filter that mainly transmits visible light and a filter that mainly transmits infrared light are arranged are alternately arranged in both a row direction and a column direction. Also, in the first unit of arrangement are arranged filters including three kinds of filters each transmitting one of red light, green light and blue light and in the second unit of arrangement are arranged four kinds of filters each transmitting one of red light, green light, blue light and infrared light.

Abstract: The present invention provides a light emitting diode (LED) lamp package structure characterized in which a plurality of light emitting diodes, a control integrated circuit, a circuit board and four electric conductivity supports are encapsulated inside a package body where the electric conductivity supports are respectively a Vdd pad, a data input pad, a data output pad, and a Vss pad. The present invention further provides a LED lamp assembly, comprising a LED lamp, a lampshade, a socket, and a mount formed with a socket. After the LED lamp is mounted on the socket with the four electric conductivity supports exposed and the socket is plugged into the socket of the mount, the electric conductivity supports would contact the four electrode contacts in the socket where the four electrode contacts are respectively a positive DC voltage electrode, a data input electrode, a data output electrode and a negative DC voltage electrode.

Abstract: A semiconductor device is described includes a wiring layer, an insulating layer stacked on the wiring layer, a trench formed by digging down the insulating layer from the surface thereof, a film-shaped lower electrode formed along the inner surface of the trench, a capacitor film formed along the surface of the lower electrode, and an upper electrode opposed to the lower electrode with the capacitor film sandwiched therebetween.

Abstract: A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic.

Abstract: Provided is a manufacturing method of a solid-state imaging device, which is able to realize a solid-state imaging device whose reflection prevention coating is even and that does not have image noise in case of adopting a spincoating method in applying a material of the reflection prevention coating onto microlenses of the solid-state imaging device. In the solid-state imaging device 1 according to the present invention, a barrier wall pattern 7 is formed, as a step alleviating structure, in dicing areas 5X formed between adjacent imaging areas 9. The barrier wall pattern 7 has a rectangular sectional form. With use of the barrier wall pattern 7 in the spincoating method, reflection prevention coating 8 is coated onto the microlenses 6 more evenly than in conventional cases.

Abstract: An integrated circuit package-in-package system including: providing a substrate; mounting a structure over the substrate; supporting an inner stacking module cantilevered over the substrate by an electrical interconnect connected to the substrate, the electrical interconnect forming a gap between the inner stacking module and the structure controlled by the size of the electrical interconnect; and encapsulating the structure and inner stacking module with an encapsulation.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes. A first drain region has a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. The first drain region and the first, second, third and fourth source regions communicate with at least two of the N plane-like metal layers. A first gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions are arranged adjacent to corners of the first drain region.