Abstract: An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycle corresponding to a predetermined odd or even number of input signal edges, with the logic optimized and protected against entry into “stuck” states. A low power, low gate count edge counter is thus implemented with an output signal duty cycle at least as balanced as the input counter duty cycle.

Abstract: To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data.

Abstract: An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2–1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves far generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2–1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2–1.5).

Abstract: An apparatus has a frequency divider accepting a clock. The frequency divider is selectable between an N divide factor and an M divide factor via a divide mode signal, where an absolute value of (N?M)=1. The apparatus also has a pulse generator responsive to a slip signal and driven by an output of the frequency divider and providing the divide mode signal to the frequency divider.

Abstract: A current conveyor circuit with improved power supply noise immunity. Additional biasing circuitry causes the nominal biasing potential applied to the output circuit to be increased, thereby producing a corresponding increase in the magnitude of noise voltage needed to appear on the power supply before the output signal becomes affected.

Abstract: A multi-phase signal generating apparatus is provided for readily generating multiple phase signals. The multi-phase signal generating apparatus comprises a signal data storage which stores a plurality of data segments for determining a predetermined period of one signal. A data segment selector circuit selects segments for constituting the phase signals from a plurality of data segments stored in the signal data storage for determining the predetermined period of a signal in each of a plurality of segment intervals which make up a phase signal cycle for generating a phase signal. Each phase signal generator circuit forms each phase signal using a plurality of selected segments for each phase signal during a plurality of segment intervals.

Abstract: A load sensing buffer circuit for providing a buffered clock signal with controlled switching current noise (di/dt) in which the input clock signal is selectively gated to provide successively generated source and sink current components as part of the buffered output signal, with the timing of such current components being dependent upon load capacitance.

Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Abstract: A trim unit includes a delay line and one or more individually selectable load elements. The delay line has a first end to receive an input clock signal, and has a second end to generate an output clock signal. Each load element includes a select transistor and a load capacitor coupled in series between the delay line and ground potential, and includes a filter circuit having an input to receive a select signal and having an output coupled to a gate of the select transistor. Upon assertion of each select signal, the filter circuit gradually charges the gate of the select transistor, which in turn causes the load element to gradually increase the phase-delay between the input and output clock signals.

Abstract: A one way conductor includes a MOSFET and a driving device. The MOSFET has a source and a drain respectively serving a positive end P and a negative end N of the one way conductor. The driving device including a BJT differential amplifier detects a voltage difference between the source and the drain of the MOSFET. When the voltage of the positive end P is higher than the voltage of the negative end N, the driving device outputs a driving voltage to a gate of the MOSFET to turn on the MOSFET. If the voltage of the positive end P is lower than the voltage of the negative end N, the driving device cannot output the driving voltage for turning on the MOSFET, and the one way conductor is turned off at this time. Consequently, the one way conductor of the invention has the one way conductive property.

Abstract: A delay locked loop capable of performing a reliable locking operation is provided that includes a phase controller, which controls a phase of a reference clock signal in response to first and second phase control signals, and a phase detector, which compares the phase of the reference clock signal to a phase of a feedback clock signal and outputs the first and second phase control signals to match the phase of the reference clock signal and the phase of the feedback clock signal, where the phase detector keeps the length of a detecting window constant in response to a current signal despite changes in external voltage, temperature, and the manufacturing process.

Abstract: An input circuit is provided which prevents malfunctioning of a function circuit during a power source voltage rise without the need of a separate Under Voltage Lock Out (UVLO) circuit.

Abstract: A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

Abstract: Methods and apparatus are provided for tuning out time constant deviations of a network (414) due to process, voltage, and temperature variations. The apparatus (400) comprises a clock reference (404) from which a digital time constant is correlated to the nominal time constant of the network (414). The correlated digital time constant is applied to the network (414), and the output charge/discharge waveform swing is compared to a predetermined reference voltage. If the charge/discharge waveform swing does not match the reference voltage, an offset signal is generated. The offset signal is applied to a control circuit (402) that generates a corresponding tuning signal. The tuning signal is applied to the network (414) to adjust the internal components incrementally until a match is achieved. The apparatus (400) can be configured as a built-in self-test digital time constant tracking circuit, and can be integrated with the network (414) on an IC chip.

Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired.

Abstract: Embodiments of the current-mode track and hold circuit comprise a cascode input stage, a dynamic biasing stage, a cascode output stage, and a switch operable to interconnect the input stage and the output stage. The input stage is connected to receive an input current. The dynamic biasing stage is connected to receive a scaled version of the input current as a dynamic biasing current and dynamically biases the input stage in response to the dynamic biasing current. Dynamically biasing the track-and-hold circuit in response to a dynamic biasing current that is a scaled version of the input current significantly increases the maximum peak-to-peak voltage swing allowed at the input of the track-and-hold circuit and enables a corresponding increase in signal-to-noise ratio. These benefits are obtained at the expense of only a small increase in power consumption.

Abstract: A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.

Abstract: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.