Abstract: An anti-cross conduction driver control circuit and method prevent the occurrence of race conditions and avoid cross-conduction between series-connected power devices, typically MOSFETs, controlled in accordance with the present invention. Individual state machines are connected across the inputs and outputs of each power device driver, and are arranged to accurately determine when the driver has completed a task requested of it. Each state machine produces a “lockout” signal based on driver status, which is used to inhibit the operation of the opposite driver under prescribed conditions, and to thereby prevent cross-conduction between the series-connected power devices.

Abstract: A drive apparatus that guarantees the stable operation of a CCD image sensor. The drive apparatus includes a drive circuit for supplying a pulse signal to the CCD image sensor. A power supply circuit is connected to the drive circuit to supply the drive circuit with a voltage for generating the pulse signal. The power supply circuit includes an over-boosting circuit for temporarily over-boosting the voltage supplied to the drive circuit to generate an over-boosted voltage, prior to the charge transfer operation of the CCD image sensor.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: A variable coupling factor directional coupler having a variable aperture positioned between a transmission line section and a coupling conductor connected at either end to a center conductor of a pair of connectors. The coupling factor of an RF signal in the transmission line section to the coupling conductor may be adjusted by linear movement of a gap plate to open or close the aperture. Alternatively, the coupling conductor may be located within a slotted tube. As the slotted tube is rotated, the slotted portion of the tube opens or closes the aperture. The position of the inner conductor of the coupling conductor with respect to a grounded sidewall can be adjusted to change the coupled line impedance in order to optimize the coupler directivity.

Abstract: In an embodiment of the invention, a charge pump circuit has a latch-up prevention circuit. The latch-up prevention circuit has a depletion P-channel MOS transistor and a resistor serially connected with each other between a negative output terminal and a ground terminal. A first bidirectional PNP-transistor is connected between a back gate of the depletion MOS transistor and the ground terminal. A second bidirectional PNP-transistor is connected between the back gate of the depletion MOS transistor and the negative output terminal. A third bidirectional PNP-transistor is between the ends of the resistor to bypass it. The base of the first bidirectional PNP-transistor is connected to the negative output terminal, the gate of the depletion MOS transistor and the bases of the second and third bidirectional PNP-transistors are connected to the ground terminal.

Abstract: A clock switching circuit suitably adapted to stable switching operation of high-frequency multiphase clock signals. The clock switching circuit receives two clock signals and selectively outputs one of the two clock signals in accordance with a selection signal. The clock switching circuit includes a switching controller that transfers the selection signal at the beginning of a period in which both of the two clock signals are active, and an internal selector that selectively outputs one of the two clock signals in response to the selection signal transferred from the switching controller.

Abstract: A logic circuit block and a memory circuit block are provided on a semiconductor chip. A timing adjustment circuit block for adjusting the propagation timing of signals is provided on a line between the circuit blocks. A timing adjustment circuit unit includes: a delay element block including a plurality of delay elements for adding different delay amounts to the inter-block signals; a counter circuit block for receiving a timing adjustment control signal from the timing adjustment circuit block; and a fuse circuit block in which a fuse is melted down based on a fuse information signal held by the counter circuit block after a timing verification and which replaces the function of the counter circuit block.

Abstract: According to an aspect of the invention, there is provided a phase synchronous circuit generating an output signal synchronized with an input signal. The phase synchronous circuit comprises an output circuit putting out an output signal according to an input clock signal, a selection circuit selecting a clock signal applied to the output circuit from multiphase clock signals such that the output circuit puts out an output signal synchronized with the input signal. The internal delay in a phase synchronous circuit using a multiphase clock signal can be efficiently compensated and an output signal synchronized with the reference signal can be generated.

Abstract: A control output signal is supplied to a gate electrode of an insulated gate transistor from a control signal output terminal of a control device, however, with regard to the insulated gate transistor, a control output signal is also influenced when that transistor is short-circuited, and a signal waveform different from that in a normal operating state occurs. The short-circuit is detected by monitoring the control output signal of the insulated gate transistor, and in case of the short-circuit, the short-circuit protection of the insulated gate transistor is performed by forcing the control device to stop that control output signal.

Abstract: A semiconductor device includes a reference voltage generation circuit, an amplifier circuit, and a voltage dropping circuit. The reference voltage generation circuit includes a negative feedback circuit to generate a reference voltage controlled by an output signal from the negative feedback circuit. The amplifier circuit amplifies the output signal from the negative feedback circuit at the leading edge of an external power supply voltage or the input time of an external signal. The voltage dropping circuit drops the external power supply voltage in accordance with the reference voltage output from the reference voltage generation circuit to generate an internal power supply voltage.

Abstract: Duty cycle correcting circuits having a gain adjusting circuit that selects one of a plurality of gains of the duty cycle correcting circuit based on a frequency of an input signal. An output circuit outputs a duty cycle corrected output signal based on the input signal and the selected one of the plurality of gains. The input signal may be an input clock signal and the output signal may be a corrected clock signal. Methods are also provided.

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Abstract: A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a reference voltage at the reference pad, and an edge-rate detection and measurement circuit coupled to the reference pad to detect and to measure an edge-rate of the reference voltage at the reference pad. Other embodiments have been claimed and described.

Abstract: Method and apparatus for locking a phase lock loop, where the method includes selecting a frequency window corresponding to a VCO output frequency, selecting a control voltage corresponding to the frequency window and providing the control voltage to the control voltage circuit which subsequently uses the selected control voltage as the starting control voltage of the phase lock loop.

Abstract: Provided is a frequency multiplier including a delay circuit, an XOR gate, and a control circuit and a method of operating such a frequency multiplier to adjust the duty cycle of a clock signal. During operation of the frequency multiplier the delay circuit receives a first clock signal and generates a delayed clock signal. The XOR gate receives the first clock signal and the delayed clock signal, performs an XOR operation on the received signals and outputs a second clock signal that has a frequency that is a multiple of the first clock signal. The control circuit monitors the phase difference between the first clock signal and the delayed clock signal and outputs a control signal corresponding to the detected phase difference to the delay circuit to adjust the time delay applied to the first clock signal by the delay circuit.

Abstract: The invention includes a phase locked loop which has a voltage-controlled oscillator, a phase comparator and a charge pump. The charge pump is coupled to a setting input of the voltage-controlled oscillator via a loop filter. A feedback input of the phase comparator is connected to the output of the voltage-controlled oscillator via a frequency divider, and the phase comparator is designed to output an actuating signal to the charge pump. The loop filter has a first charge store and at least one tunable element that alters a filter characteristic of the loop filter. In addition, there is a trimming circuit which is coupled to the at least one further element in order to alter the filter characteristic of the loop filter and which is designed to compare a time period for a charging operation in a loop filter with a reference time period.

Abstract: The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one stora

Abstract: A clock recovery circuit includes a delay locked loop, and a clock phase interpolator circuit. The delay locked loop provides multiple phases of an input clock signal to the interpolator circuit, which interpolates between two of the clock phases to provide a clock signal at a desired phase. The clock phase interpolator circuit includes selectable differential transistor pairs coupled to variable current sources. Different differential transistor pairs are driven by clock signals of different phases provided by the delay locked loop circuit. Two differential transistor pairs are selected, and currents provided to the selected differential transistor pairs are adjusted to provide an output clock of the desired phase.

Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

Abstract: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.