Abstract: An example integrated circuit includes: a substrate and a first metal fuse layer on the substrate, the first metal fuse layer having first and second electrical contacts, the first electrical contact adapted to be coupled to an input terminal, the second electrical contact adapted to be coupled to a diode. The example integrated circuit further includes a second metal fuse layer on the substrate, the second metal fuse layer having third and fourth electrical contacts, the third electrical contact coupled to the second electrical contact and adapted to be coupled to the diode, the fourth electrical contact coupled to a shunt circuit.

Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

Abstract: A driver chip for a half-bridge circuit includes a drive module and a programming module. The drive module is configured to receive an enabling signal and at least one input signal. The drive module outputs a high-side output signal to a high-side switch and a low-side output signal to a low-side switch, respectively. The programming module includes a decoding unit configured to receive the enabling signal and the at least one input signal. The programming module further includes a preset unit coupled to the decoding unit. The decoding unit outputs decoded data to the preset unit, and the preset unit outputs a circuit parameter.

Abstract: Differential-signal receivers. One example is a method of operating a differential-signal receiver, the method comprising: receiving a first differential signal on a differential-signal pair, the first differential signal accompanying a common-mode voltage that is positive relative to a reference voltage of the differential-signal receiver; clamping, when the first differential signal is positive, an OUT+ node at a first voltage; and clamping, when the first differential signal is negative, the OUT? node at a second voltage.

Abstract: An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.

Abstract: An exemplary power system includes a DC power bus and a photovoltaic system connected to the DC power bus. An energy storage system is connected to the DC power bus and stores energy injected to the DC power bus by the photovoltaic system. A power inverter is connected to the DC power bus and converts power between the DC power bus and an AC connected load. The power system also includes a control system that receives power system data from one or more sub-systems and devices connected to the DC power bus, and controls, in real-time, one or more of the power inverter and the energy storage system to act as a load on the DC power bus based on the received power system data.

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

Abstract: The application discloses a method, for building an oscillator frequency adjustment lookup table in a transceiver, wherein the transceiver generates a clock according to a crystal oscillator external to the transceiver for transceiving data. The transceiver includes adjustable capacitor arrays assembly connected to the crystal oscillator, wherein when an equivalent capacitance of the adjustable capacitor assembly is a reference value, the crystal oscillator has a reference frequency, and when the equivalent capacitance changes relative to the reference value, the crystal oscillator correspondingly has a frequency offset relative to the reference frequency. The method includes: performing an interpolation operation according to a first value, a second value, and a third value of the equivalent capacitance, and the corresponding frequency variations, so as to obtain the frequency variations corresponding to a first sub-value between the first value and the second values.

Abstract: A multi-tune filter system and a control system for operating the multi-tune filter system are described herein. The multi-tune filter system is a tunable frequency range filter. Further, the multi-tune filter system is a digitally programmable filter with an adjustable passband between first and second customizable frequency bounds f1, f2.

Abstract: A printing apparatus includes a connector configured to receive supply of first power from outside, a switch circuit configured to supply the first power to a regulator, a latch circuit configured to control the switch circuit, a power switch configured to hold the latch circuit in a predetermined state, a controller configured to hold the latch circuit in the predetermined state and to detect an operation of the power switch, and a storage configured to store setting information. In response to supply of the first power to the connector, the latch circuit is configured to, when supplied with the first power and when the predetermined state is a first state, switch on the switch circuit to supply the first power to the regulator. The regulator is configured to generate second power based on the supplied first power and to supply the second power to the controller and the storage.

Abstract: Parametrically pumped four-wave mixing is a key building block for many developments in the field of superconducting quantum information processing. However, undesired frequency shifts such as Kerr, cross-Ken and Stark shifts inherent with four-wave mixing, lead to difficulties in tuning up the desired parametric processes and, for certain applications, severely limit the fidelities of the resulting operations. Some embodiments include a Josephson four-wave mixing device consisting of a SQUID transmon coupled to a half-flux biased SNAIL transmon, a.k.a. capacitively shunted flux qubit. When the two transmon have matching frequencies, an interference effect cancels the negative Kerr of the SQUID transmon with the positive Kerr of the SNAIL transmon while preserving parametric four-wave mixing capabilities.

Abstract: In a timing signal generator having a resonator, one or more temperature-sense circuits generate an analog temperature signal and a digital temperature signal indicative of temperature of the resonator. First and second temperature compensation signal generators to generate, respectively, an analog temperature compensation signal according to the analog temperature signal and a digital temperature compensation signal according to the digital temperature signal. Clock generating circuitry drives the resonator into mechanically resonant motion and generates a temperature-compensated output timing signal based on the mechanically resonant motion, the analog temperature compensation signal and the digital temperature compensation signal.

Abstract: A conversion circuit and an adapter that resolve a voltage drop problem of a power supply of a driver in an ACF circuit. The conversion circuit includes an active clamp flyback circuit, a drive circuit, and a replenishment power transistor. The active clamp flyback circuit is configured to perform power conversion. The drive circuit is configured to output a drive signal and a reference voltage. The drive signal is used to drive the active clamp flyback circuit. A first terminal of the replenishment power transistor is coupled to an input terminal of the active clamp flyback circuit, a second terminal of the replenishment power transistor is coupled to a power supply terminal of the drive circuit, and a gate of the replenishment power transistor is configured to receive the reference voltage.

Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source.

Abstract: A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively.

Abstract: In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

Abstract: A quantum circuit includes a first qubit and a second qubit. A bus resonator transmission line is coupled between the first qubit and the second qubit. A readout bus is coupled to the first qubit. A switch is coupled to the bus resonator transmission line between the first qubit and the second qubit.

Abstract: A superconducting circuit comprises a resonator and a Josephson junction. The resonator comprises an inductor and a capacitor. The inductor comprises a first terminal and a second terminal. The second terminal of the inductor is electrically coupled to a first terminal of the capacitor. A second terminal of the capacitor is electrically coupled to a first terminal of the Josephson junction. The terminal shared by the inductor and the capacitor is configured to be electrically coupled to an alternating current (AC) voltage source having a particular frequency and particular phase. The inductance of the inductor and the capacitance of the capacitor are selected to cause the resonator to resonate at a frequency and a phase that substantially match the particular frequency and the particular phase, respectively, of the AC voltage source to facilitate switching a state of the Josephson junction via a single flux quantum (SFQ) pulse.

Abstract: Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

Abstract: An Integrated Circuit includes a target circuit, first and second logic chains, a feedback path and calibration circuitry. The target circuit includes first and second inputs. The first and second logic chains propagate a signal from a common input point to the first and second inputs of the target circuit, respectively. The feedback path receives the signal from the first or second input and feeds the signal back to the common input point. The calibration circuitry is configured to connect the first input to the feedback path thereby forming a first closed-loop oscillator circuit, and measure a first oscillation frequency of the first closed-loop oscillator circuit, connect the second input to the feedback path, thereby forming a second closed-loop oscillator circuit, and measure a second oscillation frequency of the second closed-loop oscillator circuit, and verify a timing constraint responsively to the first and second oscillating frequencies.