Abstract: Disclosed is a low-voltage detection floating N-well bias circuit. The circuit includes a power detector configured to detect states of first power (VDD) and second power (DVDD) at different power levels; a switch configured to perform a switching operation according to the states of the first power (VDD) and the second power (DVDD); and a voltage output circuit configured to output the first power (VDD) or the second power (DVDD) as an N-well bias voltage according to the states of the first power (VDD) and the second power (DVDD) and the switching operation of the switch. Accordingly, when the first power (VDD) and the second power (DVDD) are supplied and the second power (DVDD) has a low voltage state, the floating N-well bias circuit can continuously bias an N-well with the second power (DVDD), without dropping the second power (DVDD).

Abstract: A current limiting circuit of a switching circuit, and a switching circuit are provided. The switching circuit uses a gallium nitride (GaN) power transistor as a main power transistor. The current limiting circuit includes a first terminal connected with a drain of the GaN power transistor, and a second terminal connected with a controller of the switching circuit. The current limiting circuit is configured to limit a current flowing out of a power supply terminal of the controller. The current limiting circuit suppresses a negative current flowing through the controller.

Abstract: Systems and methods are provided for providing a multi-body interaction among a plurality of qubits. A first persistent current qubit is galvanically coupled to a second persistent current qubit through a Josephson junction. A third persistent current qubit is galvanically coupled to one or both of the first persistent current qubit and the second persistent current qubit along a superconducting loop interrupted by the first persistent current qubit, the second persistent current qubit, the third persistent current qubit, and the Josephson junction.

Abstract: Disclosed is a SOMA circuit having a positive input and a negative input, and which ensures that a difference of the current pulses coming from these inputs is taken and a current pulse is transmitted to an output when this difference value exceeds a threshold value.

Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.

Abstract: Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.

Abstract: A gate driver drives a gate of a semiconductor switching element. The gate driver includes a command signal output circuit, a pre-drive circuit and a drive circuit. The command signal output circuit outputs a current command signal that indicates a command value of a gate current as a current flowing through the gate of the semiconductor switching element. The pre-drive circuit receives the current command signal and generate a drive signal corresponding to the current command signal to output the drive signal. The drive circuit drives the gate of the semiconductor switching element based on the drive signal. The command signal output circuit switches the command value indicated by the current command signal while controlling a transient voltage at a desired target value. The drive circuit includes output circuits connected in parallel. Each of output circuits has at least one cascode circuit in which two MOSFETs are cascode-connected.

Abstract: A level shifter, configured to shift an input voltage swing from a first voltage range to a second voltage range, comprising a first stage and a switching stage, with circuitry configured in isolation wells. The first stage includes a first stage input receiving an input signal that swings between a first voltage value and a second voltage, a buffer configured to shift the input signal to vary between a third value and a fourth value, and a first stage output configured to present a first stage output signal. The switching stage comprises switching stage inputs, configured to receive the first stage output signal, switch drivers, and switching devices configured to, responsive to the driver output, generate a switching stage output signal that is a shifted version of the input signal. The switching stage output signal ranges between a fifth voltage value and a sixth voltage value.

Abstract: A superconducting controller for a superconducting qubit to execute high fidelity quantum gates using magnetic flux drive. The controller comprises: an inductance forming an inductive loop and configured to be inductively coupled to a qubit with a small mutual inductance; a pulse shaping circuit configured to apply a current pulse with a predefined shape across the inductance. The pulse shaping circuit comprises: a superconducting circuit configured to output single flux quanta (SFQ) pulses and a digital counter circuit configured to produce the shape of the current (magnetic flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current across the inductance by one SFQ pulse at a time.

Abstract: Embodiments provide a command processing circuit and a data processing circuit, including a plurality of flip-flops. An output terminal of a former flip-flop is connected to an input terminal of a latter flip-flop. The flip-flop is configured to sample, according to switching of a data strobe signal, an internal write command inputted into the command processing circuit to obtain a sampling command, to sample data. An output terminal of a target flip-flop is connected to a target terminal of a first flip-flop, the target flip-flop is a flip-flop whose time of outputting an active level overlaps target time, where the target time is start time and/or end time of a pulse in the internal write command. The target flip-flop is configured to reset the internal write command in the first flip-flop by outputting the active level.

Abstract: An overcurrent detection circuit including a detection unit for detecting whether a current flowing between main terminals of a main switching device used by a power conversion device is an overcurrent, and a switching unit for switching among thresholds used for determining the overcurrent in the detection unit according to in which phase of the power conversion device the main switching device is used, in which the detection unit includes a plurality of comparison units for comparing a parameter according to the current flowing between main terminals, and thresholds different from each other, and the switching unit is for switching a comparison unit to use for detection of the overcurrent among the plurality of comparison units.

Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.

Abstract: A real-time clock module includes: a timing circuit configured to measure a time to generate time data; a selection circuit configured to select at least one of a plurality of types of event data as target event data to be stored and select, as target time data to be stored, data corresponding to at least a part of time digits of the time data in response to generation of an event; and a memory circuit configured to store the target time data and the target event data.

Abstract: A charge pump comprises two bridge arms coupled in parallel, two capacitors, and a control circuit. Each bridge arm has two pairs of switches coupled in series, each pair of switches having two switches coupled in series through a common node. Each capacitor is connected between the two common nodes of the corresponding bridge arm. The control circuit provides a mode signal by comparing an output voltage of the charge pump with two threshold voltages via a hysteretic comparison, and provides two control signals with opposite logic states based on the mode signal to control each pair of the switches to work complementarily, wherein the logic states of the control signals flip in response to transiting from a first status to a second status of the mode signal, and maintain in response to transiting from the second status to the first status of the mode signal.

Abstract: A circuit arrangement and an electrical system, where in the circuit arrangement, an output terminal of a current limiting control circuit is connected to a control input of a semiconductor switch via a resistor (RG), and a gate driver is connected to the control input of the semiconductor switch via the gate resistor RG and to the resistor (R). The current limiting control circuit is configured to change its output impedance at the output terminal in order to control the semiconductor switch. A source terminal of the semiconductor switch is connected to a reference potential (GND) of the circuit arrangement, and the semiconductor switch is configured so as to set a current (I) in a circuit between an electrical power source and a load. A first inductor (L1) and a second inductor (L2) are connected in series within the circuit.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: A level shift circuitry includes a first impedance, a second impedance, a first transistor, a second transistor, a current source, and a first capacitor. The first impedance and the second impedance have a first end connected to a positive-side power supply voltage. The first transistor has a control terminal and a first end connected to a second end of the first impedance. The second transistor has a control terminal, a first end connected to a second end of the second impedance, and a second end connected to a second end of the first transistor. The current source has a first end connected to the second end of the first transistor and a second end connected to a negative-side power supply voltage. The first capacitor has a first end connected to the second end of the second impedance and a second end.

Abstract: A bio-field effect transistor (bioFET) system includes a bioFET configured to receive to a first voltage signal and output a current signal, where the current signal varies exponentially with respect to the first voltage signal. A logarithmic current-to-time converter is connected to the bioFET and is configured to receive the current signal and convert the current signal to a time domain signal. The time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.

Abstract: A quantum circuit, a quantum chip, and a quantum computer. The quantum circuit includes qubits, adjacent qubits being coupled, and each of the qubits including: a first capacitor, a first end of the first capacitor being grounded; a second capacitor, a first end of the second capacitor and the first end of the first capacitor being commonly grounded; and a first device, including a first squid and a third capacitor that are connected in parallel, wherein parallel-connected first ends of the first squid and the third capacitor are connected to a second end of the first capacitor, and parallel-connected second ends of the first squid and the third capacitor are connected to a second end of the second capacitor. According to the present disclosure, parameters of at least one of a plurality of capacitors in a qubit circuit can be adjusted, so that the design of the capacitor is more flexible and less spatially limited, which facilitates design and layout of other circuit structures.

Abstract: A semiconductor device drive circuit includes: a first transistor and a second transistor operating complementarily between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit operating between the first voltage and the second voltage, and including: a constant voltage generation unit outputting an internal power supply voltage steadily being a constant voltage; and a feedback unit receiving a node voltage of a connection node between the first transistor and the second transistor, and changing the internal power supply voltage output from the constant voltage generation unit in response to a change of the node voltage; and a pre-driver operating between the first voltage and the internal power supply voltage, and driving the first transistor or the second transistor, wherein the node voltage is output as a gate voltage of the power switching device.