Patents Examined by Tomi Skibinski
  • Patent number: 11329555
    Abstract: A voltage modulation circuit includes a charge pump circuit and a voltage detection circuit. The voltage detection circuit is coupled to the charge pump circuit. Herein, the charge pump circuit supports a plurality of power supply modes with different conversion rates and is configured to perform a power supply operation in a selected power supply mode of the power supply modes according to a control signal, to convert a power supply voltage into at least one output voltage, and to output a wake-up signal when switching of the selected power supply mode meets a specific condition. The voltage detection circuit is activated by the wake-up signal, and is configured to detect the output voltage and to suspend the power supply operation of the charge pump circuit according to a magnitude of the output voltage.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: May 10, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chih-Kang Chien
  • Patent number: 11329644
    Abstract: A gate drive apparatus is provided. The gate drive apparatus includes a gate drive unit configured to drive a gate of a switching device; a parameter measuring unit configured to measure a parameter corresponding to current flowing through the switching device; a discrepancy detection unit configured to detect discrepancy between current flowing through the switching device during an on-state of the switching device and a reference value, based on the parameter; and a control unit that, if the discrepancy is not detected, switches a change speed of a gate voltage of the switching device at a timing when a reference time has elapsed since a turn-off start of the switching device during a next turn-off time period of the switching device, and if the discrepancy is detected, keeps the change speed of the gate voltage during the next turn-off time period of the switching device.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 10, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsuyoshi Nagano, Kunio Matsubara
  • Patent number: 11329638
    Abstract: Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can have a second operational frequency, and a multi-resonant architecture can couple the first qubit to the second qubit. In various embodiments, the multi-resonant architecture can comprise a first resonator and a second resonator. In various cases, the first resonator can capacitively couple the first qubit to the second qubit, and a second resonator can capacitively couple the first qubit to the second qubit. In various aspects, the first resonator and the second resonator can be in parallel.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 10, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David C. Mckay, Abhinav Kandala, Srikanth Srinivasan
  • Patent number: 11329631
    Abstract: A tunable impedance multiplier with high multiplication factor is described. A single externally connected resistor is used and the multiplier is free of passive elements. The circuit can realize a positive or a negative impedance multiplier. Applications of the design to low and high pass filters are also presented. The simulation and experimental results show that the new design enjoys a multiplication factor above 400 at 2 Hz-to 7 MHz.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 10, 2022
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Munir Al-Absi, Muhammad T. Abuelma'atti
  • Patent number: 11323114
    Abstract: An electrical system may include a mounting surface, a component configured for connection with the mounting surface and configured to move relative to the mounting surface, and/or an orientation sensor configured to determining an orientation of the component relative to the mounting surface. The orientation sensor may include a first sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected, at least indirectly, to the mounting surface, and a second sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected to move with the component. The orientation sensor may include an electronic controller. The electronic controller may be configured to compare first information from the first sensor to second information from the second sensor to determine the orientation of the component relative to the mounting surface.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 3, 2022
    Assignee: Lear Corporation
    Inventors: Raúl Ricart, Antoni Ferré Fàbregas
  • Patent number: 11323115
    Abstract: A high-speed multiplexor comprises a set of differential input pairs to receive and mix a set of differential input signals at a differential output node pair. The high-speed multiplexer further comprises an active inductive load pair driven by the input stage using the mixed set of differential input signals. Each active inductive load comprises a p-channel field effect transistor (pFET) device connected to one of the differential output node pairs and a resistor connected between a gate node and a drain node of the pFET device. The multiplexer further comprises a first cross-coupling capacitor connected between the gate node of a first inductive load and a second output node of the differential output node pair and a second cross-coupling capacitor connected between the gate node of a second inductive load and a first output node of the differential output node pair.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 3, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaobin Yuan, Dimitrios Loizos, Varun Joshi
  • Patent number: 11316518
    Abstract: An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 26, 2022
    Assignee: PRAGMATIC PRINTING LTD.
    Inventor: Joao De Oliveira
  • Patent number: 11315746
    Abstract: A method for adjusting an optical switch keyboard and an optical switch keyboard using the adjusting method are provided. The optical switch keyboard has a number of key units. The method includes the following steps. A scan signal is applied to one of a number of scan lines by a control unit at a first scan time point. A light is emitted by a light source according to the scan signal. A light emitted by the light source is detected by a detecting element to generate a detecting electric signal. The detecting electric signal is read by the control unit to obtain a first read signal voltage. When the first read signal voltage is outside the voltage range of the pressed state of the key unit, the period of the scan signal is increased by a first predetermined amount by the control unit to obtain an adjusted scan signal.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: April 26, 2022
    Assignee: Darfon Electronics Corp.
    Inventor: Chien-Hsin Lee
  • Patent number: 11307604
    Abstract: In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Kshitij Yadav, Sherif Galal
  • Patent number: 11309871
    Abstract: A narrow pulse generation circuit used in a sequential equivalent sampling system. The circuit comprises a crystal oscillator, an edge sharpening circuit, an avalanche transistor single-tube amplifying circuit and a shaping network connected in sequence, wherein the edge sharpening circuit is used for carrying out edge sharpening on a square wave signal generated by the crystal oscillator; the avalanche transistor single-tube amplifying circuit is used for carrying out avalanche amplification on the sharpened square wave signal to generate a Gaussian pulse signal to adjust the amplitude of a pulse; and the RC shaping network is used for shaping the Gaussian pulse signal to adjust the pulse width at the bottom of the pulse to form a narrow pulse signal. The narrow pulse circuit has a simple structure and narrow pulse width at the bottom and facilitates increasing a signal-to-noise ratio of a whole sequential sampling system.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 19, 2022
    Assignee: Nantong Institute of Nanjing University of Posts and Telecommunications Co., Ltd.
    Inventors: Zhikuang Cai, Xuanchen Qi, Wenhua Lin, Guowei Shi, Jian Xiao, Yufeng Guo
  • Patent number: 11309888
    Abstract: Provided is a reverse current switch. The reverse current switch includes: a comparison unit including a first input end, a second input end, and a first output end; and a switch resistance unit, where a first end of the switch resistance unit is connected to the first input end, a second end of the switch resistance unit is connected to the second input end, and a third end of the switch resistance unit is connected to the output end of the comparison unit, and the switch resistance unit is controlled by a voltage of the first output end. This reverse current switch has a simple structure and can implement working under low voltage conditions.
    Type: Grant
    Filed: November 16, 2019
    Date of Patent: April 19, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Mengwen Zhang
  • Patent number: 11303110
    Abstract: A system and method using thyristors to protect a series-connected Flexible AC Transmission Systems (FACTS) device from surge currents are disclosed. According to some embodiments, the system includes a thyristor connected in shunt with the FACTS device to be protected. The system further includes control circuitry coupled to the thyristor to drive a gate of the thyristor with a direct current (DC) signal and turn on the thyristor in a time span on order of microseconds. The system and method can be used to protect any series-connected FACTS device that is in danger of being exposed to surge current such as a reclose after a deadline.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: April 12, 2022
    Assignee: Smart Wires Inc.
    Inventors: Amrit Iyer, Govind Chavan, Liyu Cao, Brock Petersen, Haroon Inam, Antonio Ginart
  • Patent number: 11303275
    Abstract: A system may include a power source. The power source supplies a first voltage. The system may also include a voltage regulator that receives the first voltage and supply a second voltage. Additionally, the system may include a microcontroller that receives the second voltage and output the second voltage via an output pin. Further, the system may include a switching element that receives the second voltage from the output pin of the controller at a first terminal and receives the first voltage from the power supply at a second terminal. The switching element selectively charges a first capacitor based on a difference between the first voltage and the second voltage.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: April 12, 2022
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: David W. Messersmith, William T. Glaser, Michael J. Lemberger
  • Patent number: 11303206
    Abstract: A semiconductor device disposed on a primary side of a system generating a secondary side voltage in an insulated form from a primary side voltage includes: a signal generation circuit configured to generate a voltage information signal for transmitting voltage information based on the primary side voltage to a secondary side of the system in the insulated form.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 12, 2022
    Assignee: Rohm Co., Ltd.
    Inventors: Natsuki Yamamoto, Satoru Nate
  • Patent number: 11303266
    Abstract: An electronic circuit according to the embodiment of the present invention includes a first circuit, a second circuit electrically insulated from the first circuit, and a transmitter transmitting a signal between the first and the second circuits. The first circuit receives an input signal, generates a first reference signal, and converts frequencies of the input signal and the first reference signal. The transmitter transmits the frequency-converted input signal and first reference signal to the second circuit. The second circuit converts the frequencies of the transmitted input signal first reference signal to obtain a restored input signal and a restored first reference signal, generates a second reference signal, calculates a gain to be adjusted of the restored input signal based on the restored first reference signal and the second reference signal to adjust the gain of the restored input signal.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 12, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroaki Ishihara, Satoshi Takaya
  • Patent number: 11296559
    Abstract: Provided are an apparatus and method for performing foreign object detection in a wireless power transfer system. The present specification discloses a method comprising receiving a digital ping from the wireless power transmitter; transmitting an identification and configuration packets to the wireless power transmitter; transmitting a foreign object detection (FOD) state packet which indicates a reference Q factor of the wireless power receiver to the wireless power transmitter; and receiving wireless power through magnetic coupling from the wireless power transmitter based on the foreign object detection result of the wireless power transmitter using the reference Q factor. Irrespective of individual characteristics of a wireless power receiver, accuracy and reliability of detecting a foreign object may be improved.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 5, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: Kyunghwan Kim, Yongcheol Park, Jihyun Lee, Gyunghwan Yook
  • Patent number: 11294416
    Abstract: A circuit can include a non-inverter circuit configured to generate a first clock signal with a first logic state during a first period of time in response to an input clock signal having the first logic state, and with a second logic state during a second period of time in response to the input clock signal having the second logic state. The circuit can include an inverter circuit that can be configured to generate a second clock signal with the second logic state during the first period of time in response to the input clock signal having the first logic state, and with the second logic state during the second period of time in response to the input clock signal having the second logic state.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: April 5, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Steven Elliott Mikes
  • Patent number: 11290110
    Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: March 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Borna J. Obradovic, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Mark S. Rodder
  • Patent number: 11290088
    Abstract: An apparatus includes a plurality of parallel-connected semiconductor switches (e.g., silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) or other wide-bandgap semiconductor switches) and a plurality of driver circuits having outputs configured to be coupled to control terminals of respective ones of the plurality of semiconductor switches and configured to drive the parallel-connected semiconductor switches responsive to a common switch state control signal. The driver circuits may have respective different power supplies, which may be adjustable. Respective output resistors may couple respective ones of the driver circuits to respective ones of the semiconductor switches. The output resistors may be adjustable.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: March 29, 2022
    Inventor: Geraldo Nojima
  • Patent number: 11290091
    Abstract: The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 29, 2022
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xi Chen, Xiaofeng Shen, Xingfa Huang, Liang Li, Mingyuan Xu, Jian'an Wang, Dongbing Fu, Guangbing Chen