Abstract: The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit provided with an output terminal, and configured to generate, under the control of a first control signal and a clock signal, a first differential signal according to a signal to be compared and a first reference signal; a second sampling circuit provided with an output terminal connected to the output terminal of the first sampling circuit, and configured to generate, under the control of a second control signal and the clock signal, a second differential signal according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal.

Abstract: A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.

Abstract: Bias supplies and bias control methods are disclosed. One method comprises applying an asymmetric periodic voltage waveform and providing a corresponding current waveform at an output node relative to a return node; receiving a signal to change from a current state of the asymmetric periodic voltage waveform to a next state of the asymmetric periodic voltage waveform; and adjusting, during a transition from the current state to the next state, at least one portion of the asymmetric periodic voltage waveform and simultaneously adjusting a fundamental frequency of the asymmetric periodic voltage waveform to settle at the next state.

Abstract: The invention is generally related to the field of quantum computing and particularly to a tunable resonator-resonator coupling circuit that provides both direct and indirect couplings between linear or nonlinear resonators. The indirect coupling is provided by using a tunable coupling element that comprises two ungrounded superconducting islands. Since the superconducting islands are ungrounded, it is possible to provide different signs of coupling frequencies for the resonators and the superconducting islands, which in turn allows the interaction between the first and second resonators to be controlled more efficiently. Moreover, the design, calibration, and operation of the circuit with such a tunable coupling element are significantly easier and simpler compared to the existing analogues, while providing the same or even better performance. A quantum computing apparatus using one or more such circuits is also provided.

Abstract: In described examples, a quadrature phase shifter includes digitally programmable phase shifter networks for generating leading and lagging output signals in quadrature. The phase shifter networks include passive components for reactively inducing phase shifts, which need not consume active power. Output currents from the transistors coupled to the phase shifter networks are substantially in quadrature and can be made further accurate by adjusted by a weight function implemented using current steering elements. Example low-loss quadrature phase shifters described herein can be functionally integrated to provide low-power, low-noise up/down mixers, vector modulators and transceiver front-ends for millimeter wavelength (mmwave) communication systems.

Abstract: Examples described in this disclosure relate to gating a semiconductor layer into a quantum spin Hall insulator state, Certain examples further relate to using quantum spin Hall insulators as topological quantum qubits. Quantum spin Hall systems may rely upon the quantum spin Hall effect by causing a state of a matter to change from a certain phase to an inverted bandgap phase. In one example, the present disclosure relates to a device including a semiconductor layer comprising an active material. The device further includes a gate coupled to the semiconductor layer, where the semiconductor layer is operable in a quantum spin Hall insulator state by using electrons and holes from the active material in response to an application of an electric field to the semiconductor layer via the gate.

Abstract: Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.

Abstract: The thermal sensor chip includes a substrate in which a cavity having an opening is formed, a membrane provided on a surface of the substrate so as to cover the opening, and a heater provided on or inside the membrane, wherein the heater includes wires in a mesh form constituted by a conductive member.

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

Abstract: Disclosed are a method and an apparatus for constructing a quantum circuit corresponding to a linear function. The method includes: adding an independent variable of a target linear function on a first qubit; obtaining a second qubit for outputting the target linear function, adding a parametric quantum logic gate acting on the second qubit, and controlling the parametric quantum logic gate by using the first qubit; and determining a parameter value of the parametric quantum logic gate based on the target linear function, to obtain a quantum circuit corresponding to the target linear function.

Abstract: Aspects of generating error-resistant quantum control pulses from geometrical curves are described. In some embodiments, a closed space curve is parameterized for a target gate operation of a quantum computing device. The closed space curve corresponds to an evolution operator of a time-dependent Schrödinger equation associated with the target gate operation. A control field definition is identified for the target gate operation based at least in part on a geometrical analysis of the evolution operator of the time-dependent Schrödinger equation. The target gate operation is implemented for the quantum computing device based on the control field definition.

Abstract: An enhanced bandwidth interconnect circuit. In some embodiments the circuit includes a two-terminal device and a network for forming a connection to the two-terminal device. The network may include a first set of coupled transmission lines and a second set of coupled transmission lines. A second end of the first set of coupled transmission lines may be connected to a first end of the second set of coupled transmission lines, and a second end of the second set of coupled transmission lines may be connected to the two-terminal device.

Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on th

Abstract: An electronic device for storing, controlling and manipulating electron or hole spin based semiconductor qubits, the device including an electrically insulating layer and on a front face of the insulating layer, a trapping structure for electrons or holes which includes: a channel portion including at least one layer portion of semiconductor material, as well as a plurality of gates distributed for trapping at least one electron or hole in the channel portion, and on the back side of the insulating layer, an electrical track extending parallel to the insulating layer, for generating an oscillating magnetic field acting on the at least one electron or hole trapped in the trapping structure.

Abstract: The present invention relates to an apparatus and a method for synchronizing a clock of VBE in a HVDC system capable of increasing reliability by synchronizing the clock of the VBE in the HVDC system to suppress harmonic generation and generate duplicate clock to supply stable clock to submodules. The apparatus for synchronizing the clock of the VBE in the HVDC system comprises an operation board for creating a reference clock and an interface board for controlling submodules on or off being synchronized to a reference clock.

Abstract: Several mitigation circuits are disclosed. An audio mitigation circuit includes an audio mitigation control module configured to read a unique tone identification embedded in a digital audio signal to identify a digital audio tone. A video mitigation circuit confirms video to be displayed by a user interface. Another audio mitigation circuit is configured to process super-audible tones in an audio signal to confirm an audio asset. The disclosure also describes various methods associated with the mitigation circuits.

Abstract: An integrated power control system for transferring electric power from a photovoltaic source through a power module to a transfer switch and/or a storage battery. A monitoring system includes external current sensors that control connection of the transfer switch to a utility distribution network. Electrical energy that is generated by the photovoltaic source is directed to a load and a lithium-ion storage battery according to the level of photovoltaic power generated and according to the load demand. At times when the photovoltaic energy is greater than the load demand and the charge level of the battery is at full capacity, excess energy is directed to the electrical distribution grid. In case of grid outage, energy is drawn from the battery to maintain electric supply for designated loads.

Abstract: A semiconductor device system comprises an integrated circuit (IC) die. The IC die is configured to operate in a first operating mode during a first period, and a second operating mode during a second period. The first period is associated with enabling an element of the IC die and a first amount of voltage droop. The second period occurs after the first period and is associated with a second amount of voltage droop. The second amount of voltage droop is less than the first amount of voltage droop.

Abstract: A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.

Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.