Abstract: A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively.

Abstract: In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

Abstract: A superconducting circuit comprises a resonator and a Josephson junction. The resonator comprises an inductor and a capacitor. The inductor comprises a first terminal and a second terminal. The second terminal of the inductor is electrically coupled to a first terminal of the capacitor. A second terminal of the capacitor is electrically coupled to a first terminal of the Josephson junction. The terminal shared by the inductor and the capacitor is configured to be electrically coupled to an alternating current (AC) voltage source having a particular frequency and particular phase. The inductance of the inductor and the capacitance of the capacitor are selected to cause the resonator to resonate at a frequency and a phase that substantially match the particular frequency and the particular phase, respectively, of the AC voltage source to facilitate switching a state of the Josephson junction via a single flux quantum (SFQ) pulse.

Abstract: A control signal generator includes an error amplifier, a first comparator, a second comparator, a logic circuit and a pulse generator. The error amplifier has a first output, a first input, a second input and a first snooze input. The first comparator has a second output, a third input and a fourth input. The third input is coupled to the first output. The second comparator has a third output, a fifth input, a sixth input and a second snooze input. The fifth input is coupled to the third input. The logic circuit has a fourth output and logic circuit inputs, including a first logic circuit input coupled to the second output. The pulse generator has a fifth output and a seventh input. The seventh input is coupled to the fourth output. A snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

Abstract: Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

Abstract: A composition of matter consisting primarily of a stabilizing element and a transition metal oxide, wherein the transition metal oxide is an anti-ferromagnetic Mott insulator with strong spin orbit interactions, and the composition of matter has a canted crystal structure.

Abstract: An Integrated Circuit includes a target circuit, first and second logic chains, a feedback path and calibration circuitry. The target circuit includes first and second inputs. The first and second logic chains propagate a signal from a common input point to the first and second inputs of the target circuit, respectively. The feedback path receives the signal from the first or second input and feeds the signal back to the common input point. The calibration circuitry is configured to connect the first input to the feedback path thereby forming a first closed-loop oscillator circuit, and measure a first oscillation frequency of the first closed-loop oscillator circuit, connect the second input to the feedback path, thereby forming a second closed-loop oscillator circuit, and measure a second oscillation frequency of the second closed-loop oscillator circuit, and verify a timing constraint responsively to the first and second oscillating frequencies.

Abstract: In an aspect, the present disclosure provides a superconducting circuit including: a ground plane including a superconducting member; a plurality of superconducting parts surrounded by a non-conductive part with space from the ground plane, each of the plurality of superconducting parts including four coupling ports each configured to enable the superconducting part to interact with another superconducting part; a superconducting quantum interference device configured to set a resonance frequency of a first superconducting part included in the plurality of superconducting parts; and a multilevel wiring line configured to form, in cooperation with the ground plane, a superconducting loop surrounding the superconducting quantum interference device, in which the superconducting quantum interference device is disposed, in an area inside the superconducting loop, at a place where a magnetic field generated by a current from a bias line for the first superconducting part is applied.

Abstract: A semiconductor element drive device is provided to solve a problem that because a case of a change in the temperature of the semiconductor element or a current flowing through the semiconductor element is not take into consideration, switching loss and noise cannot be reduced sufficiently. In accordance with input sensing information (temperature T, current I), a timing control unit 3 outputs a delay signal Q to control timing of driving a current increasing circuit 5 so that a reduction of switching loss of an IGBT 101 is maximized. When the IGBT 101 is in turn-on mode or turn-off mode, the current increasing circuit 5 outputs a drive signal in response to the delay signal Q delayed by a given time from output of the drive instruction signal P. In this way, the current increasing circuit 5 increases the current that causes the gate capacitor of the IGBT 101 to be charged/discharged in response to the delay signal Q, thereby increasing a switching speed to reduce switching loss.

Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.

Abstract: In a drive circuit, a differential circuit unit is configured such that resetting of an output voltage of the differential circuit unit is carried out, and the resetting of the output voltage of the differential circuit unit is cancelled. A value of the difference between first and second divided terminal voltages at a timing of cancelling the resetting is defined as a reference voltage. The differential circuit unit generates, as the output voltage, a product of a voltage change from a reference voltage and a predetermined amplification factor after cancelling of the resetting of the differential circuit unit. A signal generator generates a gate signal for the upper- and lower-arm switches in accordance with a value of the output voltage of the differential circuit unit while the upper- and lower-arm switches are in an off state.

Abstract: Techniques regarding a quantum entangling gate between multi-mode superconducting qubits are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a first multi-mode superconducting qubit coupled to a second multi-mode superconducting qubit via a transmon qubit.

Abstract: A clock signal generator and a clock signal generating method are provided. The clock signal generator is adapted for a test machine. The clock signal generator includes a first oscillator, a second oscillator, a delay value generator, and an output clock signal generator. The first oscillator and the second oscillator are activated alternatively. The first oscillator generates a first clock signal with a first frequency according to a delay value. The second oscillator generates a second clock signal with a second frequency according to the delay value, where phases of the first clock signal and the second clock signal are different. The delay value generator detects a pulse width of a reference pulse signal to generate the delay value. The output clock signal generator combines the first clock signal and the second clock signal to generate an output clock signal.

Abstract: Devices and/or computer-implemented methods to facilitate a programmable and/or reprogrammable quantum circuit are provided. According to an embodiment, a device can comprise a superconducting coupler device having a superconducting fuse device that is used to alter the coupling of a first quantum computing element and a second quantum computing element.

Abstract: Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.

Abstract: Disclosed herein is a hybrid resonant capacitor circuit including a first capacitor configured to discharge resonant current to interrupt a load current to a switch in parallel with the hybrid resonant capacitor circuit, a second capacitor coupled in parallel with the first capacitor, wherein the second capacitor is configured to transfer energy stored in the second capacitor to the first capacitor after discharge of the resonant current from the first capacitor, and a current limiter coupled in series with the second capacitor. A static transfer switch including a thyristor switch and the hybrid resonant capacitor circuit is also disclosed herein, as is a method for facilitating multiple consecutive voltage source transfers between a first voltage source and a second voltage source powering a load, using the hybrid resonant capacitor circuit.

Abstract: A device including a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

Abstract: Disclosed herein is a sensor having an extended sensing distance range beyond conventional proximity sensors. The sensor includes an electrical component structure having a topology in which current is concentrated close to a periphery of the electrical component to produce an extended sensing field. A frequency adjustment circuit can be used to control a frequency of the sensing field to avoid jammers or other interfering signals.

Abstract: Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can have a second operational frequency, and a multi-resonant architecture can couple the first qubit to the second qubit. In various embodiments, the multi-resonant architecture can comprise a first resonator and a second resonator. In various cases, the first resonator can capacitively couple the first qubit to the second qubit, and a second resonator can capacitively couple the first qubit to the second qubit. In various aspects, the first resonator and the second resonator can be in parallel.

Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.