Abstract: Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

Abstract: A system for sensing touch or proximity include: a first number of input terminals configured to couple one or more capacitive sensors, a second number of transferring units configured to transfer charges from the one or more capacitive sensors through the first number of input terminals in transferring phases of cycles of the one or more capacitive sensor, wherein at least one of the first and second numbers is equal to or greater than two, and a first switching unit, coupled between the first number of input terminals and the second number of transferring units, configured to selectively electrically couple any one of the first number of input terminals to any one of the second number of transferring units in the transferring phases.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.

Abstract: An artificial intelligence system within a network including a plurality of interconnected nodes including a first node and a second node, containing a set of interconnected nodes, a “network,” in which some nodes are externally connected, and all nodes are connected to a subset of the other nodes in such a way that the output channel of one node is connected to the input channel of another via a two-way connection, and where each node has access to the system clock, and has a classical computer (CC), and has a quantum computer (QC), and has one or more input channels, each capable of sending or receiving signals, and has one or more output channels, each capable of sending or receiving signals, and can perform a quantum computation cycle.

Abstract: The clock generation circuit outputs a clock signal with a constant cycle by repeating the following operations: when an enable signal becomes a H level, the clock signal immediately rises, and a sense end is changed to a L level via a first capacitor, then a voltage of the sense end is gradually increased via a resistor, and when the sense end reaches a predetermined potential, an output of a second inverter becomes the L level, the clock signal becomes the L level, an inverted clock signal becomes the H level, and accordingly the sense end becomes the H level; and thereafter, a current flows via the resistor so that the voltage of the sense end decreases gradually, when the sense end reaches a predetermined potential, the output of the second inverter becomes a H level, the clock signal becomes the H level, the sense end is changed to a L level via the first capacitor, then the voltage of the sense end is gradually increased via the resistor, and when the sense end reaches a predetermined potential, the out

Abstract: A current mirror circuit includes a current output terminal, a first transistor, a second transistor, and a digital-to-analog converter (DAC). The first transistor includes a first terminal coupled to a power rail, a second terminal coupled to a current source, and a third terminal coupled to the current source. The second transistor includes a first terminal coupled to the power rail, a second terminal coupled to the second terminal of the first transistor, and a third terminal coupled to the current output terminal. The DAC includes an output terminal coupled to the second transistor.

Abstract: Driver circuits to invert an input signal and to generate an output signal based on the inverted input signal are presented. The voltage level of the logical high value of the output signal is adjustable. The driver circuit has a high side switching element coupled between a supply terminal and the output terminal of the driver circuit. The driver circuit has a low side switching element coupled between the output terminal of the driver circuit and a reference potential. The driver circuit has a regulation transistor, wherein a controlled section of the regulation transistor is coupled in series with the high side switching element and the low side switching element between the supply terminal and the reference potential. The driver circuit has a feedback circuit to regulate the output voltage by generating a regulation voltage at a control terminal of the regulation transistor.

Abstract: A qubit structure includes a first fluxonium qubit having a first Josephson Junction (JJ) in parallel with a first capacitor and a first superconducting inductor. A second fluxonium qubit includes a second JJ in parallel with a second capacitor and a second superconducting inductor, coupled in series with the first fluxonium qubit. A third capacitor is coupled in parallel to the series first and second fluxonium qubits.

Abstract: Systems and methods are provided for coupling two qubits. A first persistent current qubit is fabricated with a first superconducting loop interrupted by a first Josephson junction isolated by a first inductor and a second inductor from a second Josephson junction. A second persistent current qubit is fabricated with a second superconducting loop interrupted by a third Josephson junction isolated by a third inductor and a fourth inductor from a fourth Josephson junction. Nodes defined by the Josephson junctions of the first qubit and their neighboring inductors are connected to corresponding nodes defined by the third Josephson junction and the third inductor via a first capacitor, with one pair of connections swapped such that the nodes are not connected to their respective corresponding nodes.

Abstract: Provided is a proximity sensor that can limit degradation in voltage resistance. A proximity sensor includes: a housing; a coil portion that is accommodated in one end of the housing; a clamp portion that is connected to the other end of the housing; a substrate which is accommodated inside the housing and the clamp portion, and on which a circuit electrically connected to the coil portion is mounted; a shield that covers a part of the substrate located on a side of the housing; and a resin portion which is arranged inside the housing and the clamp portion, and covers at least a part of the substrate. The shield has an extension portion which extends to an inside of the clamp portion and covers at least a part of the circuit located inside the clamp portion.

Abstract: Processor elements are disclosed herein. A processor element comprises a silicon layer. The processor element further comprises a dielectric layer disposed upon and forming an interface with the silicon layer. The processor element further comprises a conductive via in contact with the dielectric layer, the conductive via comprising a metallic portion having an interface end closest to the dielectric layer and a distal end. A cross-sectional area of the interface end of the metallic portion of the conductive via is less than or equal to 100 nm by 100 nm. In use, the application of a bias potential to the distal end of the conductive via induces a quantum dot at the interface between the dielectric layer and the silicon layer, the quantum dot for confining one or more electrons or holes in the silicon layer. Methods are also described herein.

Abstract: A device comprises first and second qubits, and a qubit coupler coupled between the first and second qubits. The second qubit comprises first and second modes with the first mode configured to store data. The qubit coupler comprises first and second modes, and operates in a first state or second state. In the first state, the first qubit is exchange coupled to the first mode of the qubit coupler, and the second mode of the second qubit is exchange coupled to the second mode of the qubit coupler, to suppress interaction between the first and second qubits. In the second state, the first qubit and the first mode of the second qubit are exchange coupled to both the first and second modes the qubit coupler, to enable interaction between the first and second qubits for an entanglement gate operation in response to a control signal applied to the qubit coupler.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

Abstract: Systems and methods are provided for resetting a qubit comprising a superconducting loop and a compound Josephson junction. A first bias flux is provided to the superconducting loop. A second bias flux is provided to the compound Josephson junction. Each of the first bias flux and the second bias flux are provided such that a given excited state of the qubit is near a top of a potential barrier associated with a potential of the qubit. A continuous microwave signal is generated having a frequency equal to a transition frequency between an other excited state of the qubit and the given excited state.

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

Abstract: Systems and methods that facilitate multilevel hysteresis voltage control methods for cascaded multilevel voltage modulators having a plurality of power cells connected in series and has any positive integer number of output voltage levels to control any unipolar voltage on the load of the voltage modulator, and transfer electrical power from an electrical grid via AC/DC converters or directly from energy storage elements of the power cells to that load. A method of operational rotation of the power cells of a multilevel voltage modulator, which ensures an equal power sharing among the power cells and voltage balancing of the energy storage elements of the power cells of the modulator.

Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Abstract: A neural processing system includes a first frontend module, a second frontend module, a first backend module, and a second backend module. The first frontend module executes a feature extraction operation using a first feature map and a first weight, and outputs a first operation result and a second operation result. The second frontend module executes the feature extraction operation using a second feature map and a second weight, and outputs a third operation result and a fourth operation result. The first backend module receives an input of the first operation result provided from the first frontend module and the fourth operation result provided from the second frontend module via a second bridge to sum up the first operation result and the fourth operation result.