Abstract: A substrate member includes a substrate and a plurality of chip regions formed on the substrate across a scribe line. Each of the plurality of chip regions includes a first region that has contact with the scribe line and in which a plurality of first pattern elements are formed, and a second region that is surrounded by the first region and in which a plurality of second pattern elements are formed. A minimum value of a size of the first pattern elements is greater than a minimum value of a size of the second pattern elements and/or a minimum value of an interval between adjacent first pattern elements is greater than a minimum value of an interval between adjacent second pattern elements.

Abstract: A radio frequency (RF) module comprises an electrical reference, or ground, plane to which one or more RF devices disposed on the module are electrically coupled, and may be disposed beneath the RF devices. The reference plane may be segmented as to form one or more segments of the reference plane that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated reference planes, correspond to different devices of the module. The reference plane may be etched or cut to achieve such segmentation.

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region.

Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.

Abstract: The disclosure is directed to laser annealing of GaN light-emitting diodes (LEDs) with reduced pattern effects. A method includes forming elongate conductive structures atop either an n-GaN layer or a p-GaN layer of a GaN LED structure, the elongate conductive structures having long and short dimensions, and being spaced apart and substantially aligned in the long dimensions. The method also includes generating a P-polarized anneal laser beam that has an anneal wavelength that is greater than the short dimension. The method also includes irradiating either the n-GaN layer or the p-GaN layer of the GaN LED structure through the conductive structures with the P-polarized anneal laser beam, including directing the anneal laser beam relative to the conductive structures so that the polarization direction is perpendicular to the long dimension of the conductive structures.

Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

Abstract: A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.

Abstract: The present invention provides an organic electroluminescence device and a manufacturing method thereof. The organic electroluminescence device includes: an organic backing layer (22), which provides a flexible base and isolates external moisture; a light absorption layer (24), which is arranged on the organic backing layer (22); an active thin-film transistor pixel array, which is arranged on the light absorption layer (24), the active thin-film transistor pixel array comprising at least a crystalline semiconductor layer that is formed by means of laser annealing; and an organic electroluminescence layer (29), which is arranged on the active thin-film transistor pixel array. The light absorption layer (24) absorbs the laser that transmits through the active thin-film transistor pixel array and irradiates the light absorption layer (24) during the laser annealing in order to prevent the organic backing layer (22) from being affected by the laser and getting deteriorated.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through the adhesive layer and are connected to the TSVs and the active layer. Side surfaces of the adhesive layer are aligned with side surfaces of the second semiconductor chip.

Abstract: An image sensor includes a pixel layer in which an active pixel array and an optical black pixel array are formed; a first anti-reflective layer which is formed over the active pixel array, and including a hafnium oxide layer with a high transmittance; and a second anti-reflective layer which is formed over the optical black pixel array, and including a hafnium oxide layer with a low transmittance.

Abstract: A chip on film for a flexible display device is disclosed. In one aspect, the chip on film includes a base film, a semiconductor chip provided to the base film, and a wire part provided to the base film and electrically connected to the semiconductor chip. The wire part includes a first region and a second region connected to the first region, and a first interval between the wires disposed at an outermost of the first region is different from a second interval between the wires disposed at an outermost area of the second region.

Abstract: An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.

Abstract: A method of forming a ferroelectric capacitor includes forming inner conductive capacitor electrode material over a substrate. After forming the inner electrode material, an outermost region of the inner electrode material is treated to increase carbon content in the outermost region from what it was prior to the treating. After the treating, ferroelectric capacitor dielectric material is formed over the treated outermost region of the inner electrode material. Outer conductive capacitor electrode material is formed over the ferroelectric capacitor dielectric material.

Abstract: There are provided semiconductor packages having corner pins and methods for their fabrication. Such a semiconductor package includes a leadframe and a die paddle, the leadframe having first and second edge sides meeting to form a first corner. The semiconductor package also includes edge pins arrayed substantially parallel to the first edge side and edge pins arrayed substantially parallel to the second edge side. In addition, the semiconductor package includes a first corner pin situated at the first corner, the first corner pin being electrically isolated from the die paddle.

Abstract: A 3D semiconductor device is provided, comprising memory layers, a selection line, bit lines, strings, memory cells defined by the strings, the selection line, and the bit lines, wherein the memory cells are arranged in a plurality of rows having a first direction, and a stair contact structure including stair contacts and conductive lines, wherein the stair contacts are arranged in a plurality of columns having a fourth direction. The 3D semiconductor device satisfies the following condition: 1<A?10 and 1<B?30; wherein A is the number of the rows of the memory cells in the selection line or A=a/XBL, a is a memory cell pitch and XBL is a bit line pitch along the first direction, B is the number of the columns of the stair contacts or B=YSC/YD, and YSC is a stair contact pitch and YD is the conductive line pitch along the fourth direction.

Abstract: The present invention generally relates to devices comprising graphene and a conductive polymer (e.g., poly(3,4-ethylenedioxythiophene) (PEDOT)), and related systems and methods. In some embodiments, the conductive polymer is formed by oxidative chemical vapor deposition.

Abstract: An optoelectronic device comprises a semiconductor stack having a first surface, a contact layer having a first pattern on the first surface for ohmically contacting the semiconductor stack, a void in the semiconductor stack and surrounding the contact layer, and a mirror structure on the first surface and covering the contact layer, wherein the first surface has a first portion which is not covered by the contact layer and a second portion covered by the contact layer, and the first portion is rougher than the second portion.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: A non-coherent light emitting device having at least one organic light emitting or organic charge transporting layer and a structure providing a Bragg grating associated with the light emitting layer is described. The organic light emitting layer having liquid crystalline material is treated to provide alternating zones of isotropic and liquid crystalline material. The combination of alternating zones with the dichroic effects of the aligned zone produces a pseudo 2-D Bragg grating within the light emitting layer.