Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Abstract: A package stacked device may include a first packaging body layer having a first chip embedded therein, and a second packaging body layer positioned under the first packaging body layer and having a second chip embedded therein. The package stacked device may also include a first connection unit protruding from a first bottom surface of the first packaging body layer, a second connection unit protruding from a second top surface of the second packaging body layer, a first covering layer providing a first opening to expose the top surface of the second connection unit and substantially covering the second top surface of the second packaging body layer, and a first adhesive layer substantially covering the exposed top surface of the second connection unit within the first opening. The first connection unit may be inserted into the first opening and connected to the first adhesive layer.

Abstract: A universal lead frame for semiconductor packages includes a solid lead frame sheet comprising an electrically conductive material and a plurality of columns etched into the lead frame sheet and distributed with a predetermined lead pitch so that the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing the universal lead frame includes providing a solid lead frame sheet of an electrically conductive material and etching a plurality of columns into the lead frame sheet so that the columns are distributed with a predetermined lead pitch and the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing molded semiconductor packages using the universal lead frame is also provided.

Abstract: A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.

Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.

Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.

Abstract: A semiconductor memory device according to an embodiment includes a stacked body with electrode films and inter-electrode insulating films alternately stacked therein, a semiconductor member, a charge accumulation film, an insulating member and a floating electrode member. The semiconductor member is provided in the stacked body. The insulating member is provided at a position opposed to the inter-electrode insulating film on a side surface of the charge accumulation film. The insulating member is divided for each of the inter-electrode insulating films. The floating electrode member is provided on a region of the side surface of the charge accumulation film not covered with the insulating member. The floating electrode member is in contact with the charge accumulation film. The floating electrode member is divided for each of the electrode films. The floating electrode member has higher conductivity than the charge accumulation film.

Abstract: A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode.

Abstract: A method of fabricating an optoelectronic device, comprises: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a light emitting stack on the second major surface of the substrate; forming a supporting layer covering the light emitting stack; forming a plurality of first modified regions in the substrate by employing a first energy into the substrate after forming the supporting layer; and cleaving the substrate.

Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.

Abstract: A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. The semiconductor device further includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided. A semiconductor device comprises a substrate, a conductive pattern formed on the substrate, and at least a conductive pillar having a predetermined height formed on the conductive pattern. The conductive pillar can be formed under a focus ion beam (FIB) or an electron beam environment. In one embodiment, a diameter of the conductive pillar is no more than 10 ?m.

Abstract: A transistor includes: a gate electrode; a semiconductor layer facing the gate electrode with an insulating layer in between; a pair of source-drain electrodes electrically connected to the semiconductor layer; and a contact layer provided in a moving path of carriers between each of the pair of source-drain electrodes and the semiconductor layer, the contact layer having end surfaces covered with the source-drain electrode.

Abstract: A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or more RF devices disposed on the module. The RF-shielding may comprise wirebond structures disposed adjacent to or surrounding an RF device. Two or more intramodule devices may have wirebond structures configured to at least partially block certain types of RF signals disposed between the devices, thereby reducing effects of cross-talk between the devices.

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract: A photomask has a mask blank and a light shielding film formed on the mask blank. The light shielding film includes a plurality of opening traces extending in a first direction. An end of a first opening trace in the first direction and an end of a second opening trace in the first direction are in different positions in the first direction. The second opening trace adjoins the first opening trace.

Abstract: An electrical component includes a closed lead frame with a passage opening at least one electrical component arranged within the passage opening, the electrical component including a first contact pad on one side of the electrical component and a second contact pad on a second side of the electric component, wherein the second side faces the first side and the second contact pad is electrically coupled to the lead frame; and an encapsulation which mechanically couples the electrical component to the lead frame, wherein the lead frame includes a recess on one side, the recess extending from an edge of the lead frame to the passage opening and connecting at least one electrical connecting element from the edge of the lead frame to the component arranged in the passage opening.

Abstract: A radio frequency (RF) module comprises a conductive top layer configured to improve RF interference-shielding functionality with respect to one or more RF devices disposed on the module. The conductive top layer may be segmented as to form one or more segments of the top layer that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated, top conductive layers correspond to different devices of the module. The top layer may be etched or cut to achieve such segmentation.

Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.