Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Abstract: Disclosed herein is a semiconductor package that includes: a package substrate having a main surface; a plurality of semiconductor devices mounted on the main surface of the package substrate; a mold member formed on the main surface of the package substrate so as to cover the semiconductor devices, the mold member having an upper surface substantially parallel to the main surface of the package substrate; and an electromagnetic wave shield formed on the upper surface of the mold member. The mold member comprises a mold resin and metal magnetic particles dispersed in the mold resin. The metal magnetic particles are exposed to the upper surface of the mold member.

Abstract: A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.

Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

Abstract: A light emitting device includes a base member including a conductive member; a light mining element arranged on the base member, the light emitting element having a first surface, a second surface opposing the first surface, and at least one lateral surface between the first surface and the second surface; a die-bonding resin bonding the base member and the second surface; a first protective film continuously covering the base member, the die-bonding resin, the at least one lateral surface, and the first surface; and a second protective film continuously covering the base member, the die-bonding resin, the at least one lateral surface and the first surface of the light emitting element, over the first protective film, the second protective film having a linear expansion coefficient that is smaller than a linear expansion coefficient of the die-bonding resin and larger than a linear expansion coefficient of the first protective film.

Abstract: Collateral etching of a dielectric material around a trench during formation of a substrate contact via structure can be avoided employing an aluminum oxide layer. The aluminum oxide layer functions as an etch stop layer during an anisotropic etch that removes horizontal portions of an insulating material layer to form an insulating spacer. The aluminum oxide layer may be a conformal or a non-conformal material layer, and may, or may not, include a horizontal portion that overlies an alternating stack of insulating layers and electrically conductive layers. Electrical shorts caused by widening of the top portion of the trench can be avoided through use of the aluminum oxide layer. Memory stack structures can extend through the alternating stack to provide a three-dimensional memory stack structure. A source region can be formed underneath the trench, and the substrate contact via structure can be employed as a source contact via structure.

Abstract: A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

Abstract: A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The antistatic die attach material includes a mixture of a nonconductive adhesive material and carbon black or graphite. In one example, the antistatic die attach material has a resistivity between 101 ?·cm and 1010 ?·cm.

Abstract: A semiconductor light emitting device including an N-type semiconductor layer, a P-type semiconductor layer, a light emitting layer and a strain relief layer is provided. The light emitting layer is disposed between the N-type semiconductor layer and the P-type semiconductor layer, and the light emitting layer is a multiple quantum well structure. The strain relief layer is disposed between the light emitting layer and the N-type semiconductor layer, and is made of InxGa1-xN, where 0<x<1. The difference between any two values of x corresponded to any two positions in the strain relief layer is greater than ?0.01 and less than 0.01. The thickness of the strain relief layer is larger than the thickness of each well layer of the multiple quantum well structure.

Abstract: Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area.

Abstract: A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well.

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.

Abstract: A MOSFET includes: a SiC layer including one main surface and provided with a plurality of contact regions; and a plurality of source electrodes formed in contact with the contact regions. In the MOSFET, in a plan view of the one main surface, a plurality of cells including the contact regions and the source electrodes are formed adjacent to one another, each of the plurality of cells having an outer circumferential shape that is a shape of hexagon including a long axis. According to the MOSFET, a contact resistance between each contact region and each source electrode can be further reduced, thereby attaining a more improved electrical property.

Abstract: A transistor with stable electrical characteristics is provided. The transistor includes a first insulator over a substrate; first to third oxide insulators over the first insulator; a second insulator over the third oxide insulator; a first conductor over the second insulator; and a third insulator over the first conductor. An energy level of a conduction band minimum of each of the first and second oxide insulators is closer to a vacuum level than that of the oxide semiconductor is. An energy level of a conduction band minimum of the third oxide insulator is closer to the vacuum level than that of the second oxide insulator is. The first insulator contains oxygen. The number of oxygen molecules released from the first insulator measured by thermal desorption spectroscopy is greater than or equal to 1E14 molecules/cm2 and less than or equal to 1E16 molecules/cm2.