Patents Examined by Tri Hoang
  • Patent number: 10217495
    Abstract: Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventor: Jaydeep Kulkarni
  • Patent number: 10210915
    Abstract: A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M0 (M0 is an integer greater than or equal to 2), a global sense amplifier array, M0 local memory cell arrays <1> to <M0>, and M0 local sense amplifier arrays <1> to <M0>. A memory cell includes a transistor and a capacitor. A local memory cell array <J> (J is an integer from 1 to M0) is stacked over a local sense amplifier array <J>. The local memory cell array <J> comprises M0 blocks <J_1> to <J_M0> differentiated by row, The local sense amplifier array <J> in an idle state retains the data of the block <J_J>. The block <J_J> is specified when the local memory cell array <J> is the first local memory cell array to be accessed in a burst read mode.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Onuki
  • Patent number: 10204686
    Abstract: A page buffer includes a first precharge circuit, a second precharge circuit, and a sense amplifying circuit. The first precharge circuit includes a first path for precharging a bitline connected to a nonvolatile memory cell. The second precharge circuit includes a second path for precharging a sensing node connected to the bitline. The second path is electrically separated from the first path. The sensing node is used to detect a state of the nonvolatile memory cell. The sense amplifying circuit is connected to the sensing node and the second precharge circuit, and stores state information representing the state of the nonvolatile memory cell. The second precharge circuit is configured to perform a first precharge operation for the sensing node and configured to selectively perform a second precharge operation for the sensing node based on the state of the nonvolatile memory cell after the first precharge operation.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Yun Lee, Chae-Hoon Kim
  • Patent number: 10204672
    Abstract: A magnetic memory device includes a memory cell array, a counter circuit and a control circuit. The memory cell array includes a memory cell including a magneto resistive element in which writing is performed by current in a first direction or current in a second direction which is an opposite direction to the first direction. The memory cell array includes a first word line and a first bit line, both connected with the memory cell. The counter circuit counts the number of writing times in the first direction while the counter circuit is in electrical connection with the magneto resistive element. The control circuit performs writing in the second direction in the memory cell when the number of consecutive writing times in the first direction reaches a threshold number of times while the control circuit is in connection with the memory cell array.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Kobayashi
  • Patent number: 10192629
    Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yunchen Qiu, David J. Toops, Harold L. Davis
  • Patent number: 10161566
    Abstract: In one embodiment, a power tool includes a cutting assembly, a sensor system proximate to the cutting assembly, a reaction system operably connected to the cutting assembly, a memory, program instructions stored within the memory, a spatial recognition algorithm stored within the memory, and a processor operably connected to the reaction system, the sensor system, and the memory. The processor is configured to execute the program instructions to detect a man profile within a detection zone associated with the cutting assembly, establish a location of the human profile within the detection zone based upon the detection using the spatial recognition algorithm, determine that an unsafe condition exists based upon the established location, and activate the reaction system.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: December 25, 2018
    Assignees: Robert Bosch Tool Corporation, Robert Bosch GmbH
    Inventors: Gary L. Voong, Robert Lewis Newton, John Seo
  • Patent number: 10163485
    Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Patent number: 10162538
    Abstract: A data storage device includes a controller and a memory. The memory is coupled to the controller. The memory includes storage elements coupled to bit lines. The controller is configured to access bit line integrity data corresponding to a region of the memory, the bit line integrity data indicating a number of bit lines. The controller is also configured to store data related to a memory operation threshold based on the number of bit lines.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mark Shlick, Refael Ben-Rubi, Uri Shir, Ahiad Turgeman, Uri Peltz
  • Patent number: 10153006
    Abstract: A semiconductor device includes semiconductor chips stacked each other. Each of the semiconductor chips converts second reception data received by second reception terminals arranged in point symmetry on the first face by a conversion method to convert first reception data received by first reception terminals arranged in point symmetry on the first face into a reference data; and generates an identification information of the each semiconductor chip based upon the converted second reception data; and outputs the bit sequence obtained by converting the generated identification information by means of the inverse conversion method of the conversion method.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 11, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yusuke Hamada
  • Patent number: 10153013
    Abstract: A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. The data output buffer may include a pull-up driver configured to output the pull-up drive signal by driving a pull-up signal, and selectively activate the pull-up drive signal based on the pull-up feedback signal. The data output buffer may include a pull-down circuit configured to output a pull-down feedback signal by pull-down driving the output node based on a pull-down drive signal. The data output buffer may include a pull-down driver configured to output the pull-down drive signal by driving a pull-down signal, and selectively activate the pull-down drive signal based on the pull-down feedback signal.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 11, 2018
    Assignee: SK hynix Inc.
    Inventor: Mi Hyun Hwang
  • Patent number: 10147359
    Abstract: A display driver includes a plurality of output terminals that output a plurality of data signals which are output to an electro-optical panel, a plurality of capacitance circuits that are respectively provided between adjacent output terminals of the plurality of output terminals, and a control circuit that sets capacitance values of each capacitance circuit.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 4, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Patent number: 10147764
    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Andrea Redaelli
  • Patent number: 10147493
    Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Parvinder Kumar Rana, Lava Kumar Pulluru, Manish Chandra Joshi
  • Patent number: 10141044
    Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 27, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Patent number: 10127989
    Abstract: An object of the present disclosure is to provide a semiconductor having high security. A semiconductor device includes: a memory region having a plurality of memory cells capable of storing data; a read circuit capable of switching a reference current reading method of reading data by comparing current flowing a memory cell to be read in the memory region with a reference current, and a complementary reading method of reading data by comparing currents flowing in first and second memory cells in which complementary data to be read in the memory region is stored; a register setting a security state; a mode controller setting a mode; and a control circuit controlling the reference current reading method and the complementary reading method of reading the data in the read circuit on the basis of a signal of setting a mode from the mode controller and a value of the register.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Kurafuji
  • Patent number: 10127956
    Abstract: A magnetic memory device may include tunnel junction unit cells, each including a pinned magnetic layer, an insulating layer, and a free magnetic layer which are sequentially stacked, a conductive line structure configured to supply an in-plane current to the unit cells and to include an antiferromagnetic layer, which is provided adjacent to the free magnetic layer, and a ferromagnetic layer, which is provided adjacent to the antiferromagnetic layer and has an in-plane magnetic anisotropy, and a voltage applying unit configured to independently apply a selection voltage to each of the tunnel junction unit cells. Each of the tunnel junction unit cells may have a magnetization direction that is selectively changed by the in-plane current and the selection voltage.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 13, 2018
    Assignee: Korea University Research and Business Foundation
    Inventors: Kyung Jin Lee, Hyun Woo Lee, Byong Guk Park
  • Patent number: 10109362
    Abstract: A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 23, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jeong-Tae Hwang
  • Patent number: 10090706
    Abstract: An apparatus, network system, and method for detecting network phenomena of a power distribution network. A signal injection device adapted to be connected to the power distribution network injects a signal having signal parameters onto the power distribution network. A signal receiving device adapted to be connected to the power distribution network receives the injected signal on the power distribution network. The signal receiving device is adapted to determine the signal parameters of the received signal and is adapted to evaluate the signal parameters of the injected signal with respect to the determined signal parameters of the received signal. An output device connected to the signal receiving device provides an indication of the determined evaluation.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: October 2, 2018
    Assignee: Aclara Technologies LLC
    Inventor: David W. Rieken
  • Patent number: 10083726
    Abstract: An input circuit may include: an internal bias generation unit suitable for generating first and second bias voltages in response to a first enable signal; a buffer control unit suitable for comparing a reference voltage to the first and second bias voltages, and generating a plurality of buffer control signals based upon the comparison of the reference voltage with the first and second bias voltages; and a buffer unit including a plurality of buffers, wherein a buffer is driven to receive the reference voltage and an external input signal, and generates an internal signal, in response to an activated buffer control signal among the plurality of buffer control signals.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: September 25, 2018
    Assignee: SK Hynix Inc.
    Inventor: Yeonsu Jang
  • Patent number: 10083721
    Abstract: A method for reducing susceptibility to vibration for a storage device is provided. The method includes running a performance test to the storage device over a predetermined range of vibration frequencies and determining there is a frequency of concern for the storage device. The method also includes establishing resonant frequencies of the storage device and determining if a resonant frequency of the storage device corresponds to the frequency of concern. If a resonant frequency corresponds to the frequency of concern, then the method includes reducing stiffness of a plurality of mounting members coupled to the storage device and repeating running the performance test, determining there is a frequency of concern, determining a resonant frequency overlaps a frequency of concern, and reducing stiffness of the plurality of mounting members until one of there are no frequencies of concern and a resonant frequency does not correspond to a frequency of concern.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 25, 2018
    Assignee: Seagate Technology LLC
    Inventors: Christopher Ellis Schroeder, Charles Powell Morris, Kevin Lee Van Pelt