Abstract: A non-volatile memory system includes a plurality of groups of connected non-volatile memory cells (e.g., charge trapping memory cells), a select line, and a plurality of select gates connected to the select line. Each select gate is connected at an end (e.g. source end or drain side) of one of the groups of memory cells. The system includes one or more control circuits that are configured to determine whether the select gates are abnormal. If a select gate is determined to be abnormal, then one of the memory cells connected to the select gate is converted to operate as a select gate. The system will then perform memory operations by operating the converted memory cell as a select gate.

Abstract: Magnetic memory devices having an antiferromagnetic reference layer based on Co and Ir are provided. In one aspect, a magnetic memory device includes a reference magnetic layer having multiple Co-containing layers oriented in a stack, wherein adjacent Co-containing layers in the stack are separated by an Ir-containing layer such that the adjacent Co-containing layers in the stack are anti-parallel coupled by the Ir-containing layer therebetween; and a free magnetic layer separated from the reference magnetic layer by a barrier layer. A method of writing data to a magnetic random access memory device having at least one of the present magnetic memory cells is also provided.

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

Abstract: The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures.

Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

Abstract: According to one embodiment, the semiconductor memory device includes a memory element, a reference resistance element, a read circuit, and a first circuit. The memory element is enabled to take a first resistance value and a second resistance value. The reference resistance element configured to have a resistance value between the first resistance value and the second resistance value. The read circuit is configured to determine data read from the memory element based on a current flowing through the memory element and a current flowing through the reference resistance element. The first circuit is configured to suppress the currents flowing through the memory element and the reference resistance element in response to determination of data read from the memory element.

Abstract: An example method to track bit cell current in a memory architecture. An example method disclosed herein includes generating a first reference current dependent on bit cell temperature. The example method includes generating a second reference current dependent on bit cell voltage and supplying a third reference current of constant magnitude. In examples disclosed herein, the example method involves summing the first reference current, the second reference current, and the third reference current. The example method includes determining, with a sense amplifier, a bit cell logic state based on the first reference current, the second reference current, and the third reference current.

Abstract: A semiconductor device and a method of operating the same are provided. The method includes performing a program operation on a memory cell so that a threshold voltage of the memory cell is greater than a main verifying voltage, and while the program operation is performed, a bit line voltage applied to a bit line connected to the memory cell gradually increases based on the threshold voltage of the memory cell and the number of times a program voltage is applied to a word line connected to the memory cell.

Abstract: A non-volatile semiconductor memory device having an improved layout structure to achieve low power consumption, high speed and miniaturization is provided. A flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. A plurality of local bit lines are shared by each of the plurality of blocks in one global block, a plurality of global bit lines are shared by the plurality of global blocks, and a connecting element selectively connecting one global bit line to n local bit lines is included. When a read-out operation and program operation are executed, one global bit line is shared by n local bit lines.

Abstract: A 6T bitcell for single port SRAM that performs single ended read and single ended write is described. The presently described bitcell gives huge advantage in terms of area, dynamic power, leakage power and performance over the prior art in the industry. The bitcell and architecture does not have either a write bitline pair or a read bitline for each bitcell. It has only one read bitline per mux.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Abstract: A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal as soon as the comparison flag signal is enabled.

Abstract: A data processing device includes a data processing unit including a plurality of elements and wiring groups that connect the plurality of elements, wherein respective elements in the plurality of elements include: a logic element; an acquisition unit that switches on and off an input side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis to latch input data; and a post unit that switches on and off an output side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis, and the data processing unit also includes a timing control unit that controls logic executed by the logic element and functions of the acquisition unit and the post unit on a cycle-by-cycle basis.

Abstract: A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

Abstract: A magnetic memory includes a magnetic thin line including a plurality of magnetic domains, a reference layer having a magnetization, a nonmagnetic layer, a first fixed magnetization part having a magnetization, a second fixed magnetization part having a magnetization, a first electrode, a second electrode, and a third electrode.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit line pairs. Firstly, the plural bit line pairs are precharged to a precharge voltage. Then, a selected memory cell connected with a specific bit line pair is determined. Then, two bit lines of the specific bit line pair are respectively connected with the data line and the reference line and are discharged to a reset voltage. After a first cell current and a second cell current from the specific bit line pair are received, a first voltage level of the data line and a second voltage level of the reference line are gradually changed from the reset voltage. According to a result of comparing the first voltage level and the second voltage level, an output signal is generated.

Abstract: A bit cell and memory architecture wherein a write bitline is not required is presented. The bitcell and the memory architecture bring a huge improvement in the performance, dynamic power, leakage power, area, and the yield of the memory.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs first to (M+1)th command/address signals (wherein, “M” denotes a natural number which is equal to or greater than two) and receives a detection signal to detect a normality/abnormality of a temperature sensor. The second semiconductor device enters a test mode in response to the (M+1)th command/address signal and compare first to Nth sensing codes (wherein, “N” denotes a natural number which is equal to or greater than two) generated by the temperature sensor with the first to Mth command/address signals to generate the detection signal. The second semiconductor device also executes a refresh operation in response to a refresh signal including a plurality of pulses whose cycle time is controlled by the first to Mth command/address signals.