Abstract: An input circuit may include: an internal bias generation unit suitable for generating first and second bias voltages in response to a first enable signal; a buffer control unit suitable for comparing a reference voltage to the first and second bias voltages, and generating a plurality of buffer control signals based upon the comparison of the reference voltage with the first and second bias voltages; and a buffer unit including a plurality of buffers, wherein a buffer is driven to receive the reference voltage and an external input signal, and generates an internal signal, in response to an activated buffer control signal among the plurality of buffer control signals.

Abstract: A method of configuring actual Intelligent Electronic Devices (IEDs) into a substation automation system (SAS) of a power system that runs a substation process. An IED data repository stores IED information including a plurality of logical node classes (LNs), where each LN includes a plurality of data objects as LN type definitions that represent at least bay level functions including control and monitoring outputs from the primary devices or protecting the primary devices. Using an LN type generator, selection of LNs is performed from the plurality of LNs based on functions for implementing at least one single line diagram (selected LNs) that represents the SAS. From the selected LNs a pre-configured IED strategy is generated to represent at a first actual IED to control and automate the substation process in a format understood by the SAS. The pre-configured IED strategy is saved into the IED data repository.

Abstract: A method includes obtaining information associated with multiple events in an industrial process control and automation system, where the information is obtained from one or more sources of data related to the industrial process control and automation system. The method also includes outputting the information to a notification system configured to generate multiple notifications for mobile end-user devices using the retrieved information. Obtaining the information associated with the multiple events includes using one or more queries to obtain at least part of the information from at least one of the one or more sources. The one or more queries support detection of events from the at least one source that is not configured or able to provide event information to the notification system.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL1, WL2, the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.

Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.

Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

Abstract: A semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory cells programmed to any one of first to N-th program states divided based on threshold voltages. The peripheral circuit may perform a program operation on the memory cells. The control circuit may control the peripheral circuit so that, during the program operation, a primary program operation is performed, and after the primary program operation, a secondary program operation is performed. The primary program operation may include a plurality of verify steps performed for the first to N?1-th program states and a single primary verify step performed for the N-th program state. The secondary program operation may include a secondary verify step performed for the N-th program state.

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Abstract: A fault detection module acquires Spread Spectrum Time Domain Reflectometry (SSTDR) data pertaining to an electrical system, such as a photovoltaic string. A fault may be detected by use of difference data, calculated by comparing the SSTDR autocorrelation data to baseline SSTDR autocorrelation data previously acquired from the electrical system. The cumulative difference in the SSTDR autocorrelation data may indicate the presence of a fault and/or the location of the fault within the electrical system.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Abstract: A non-volatile memory device for selectively performing a recovery operation and a method of operating the same are provided. The method of operating a non-volatile memory device includes receiving a first read command, performing a first sensing operation in response to the first read command, and receiving a second read command. The method further includes completing a memory operation corresponding to the first read command without performing a recovery operation when the second read command is received before the first sensing operation is completed, and performing a second sensing operation in response to the second read command.

Abstract: A method of controlling a magnetization state using an imprinting technique may be provided. The method may include moving first and second magnetic structures, which have different magnetization states, toward each other and changing a magnetization state of the first or second magnetic structure, when a distance between the first and second magnetic structures is reduced. A magnetic field, which is produced by a magnetization state of one of the first and second magnetic structures, may be used to align a magnetization state of the other, when the magnetization state of the first or second magnetic structure is changed.

Abstract: A semiconductor system may include a first semiconductor apparatus, and a second semiconductor apparatus. The first semiconductor apparatus may be configured to transmit a first system clock signal and a second system clock signal having a first frequency, and transmit a data strobe signal having a second frequency. The second semiconductor apparatus may include a clock multiplier configured to generate a read data strobe signal having the second frequency, based on the first and second system clock signals.

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

Abstract: A data processing device includes a data processing unit including a plurality of elements and wiring groups that connect the plurality of elements, wherein respective elements in the plurality of elements include: a logic element; an acquisition unit that switches on and off an input side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis to latch input data; and a post unit that switches on and off an output side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis, and the data processing unit also includes a timing control unit that controls logic executed by the logic element and functions of the acquisition unit and the post unit on a cycle-by-cycle basis.

Abstract: A memory device may include N memory areas that are divided into a first group and a second group, and are selected by area selection signals corresponding to the N memory areas among N area selection signals, N*M pipe latches that store output data of memory areas corresponding to the N*M pipe latches among the N memory areas, a first pipe output signal generation circuit that generates 1-1th to 1-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the first group, in response to an area selection signal corresponding to a predetermined memory area of memory areas, and a second pipe output signal generation circuit that generates 2-1th to 2-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the second group, in response to an area selection signal corresponding to a predetermined memory area of memory areas.

Abstract: An object of the present disclosure is to provide a semiconductor having high security. A semiconductor device includes: a memory region having a plurality of memory cells capable of storing data; a read circuit capable of switching a reference current reading method of reading data by comparing current flowing a memory cell to be read in the memory region with a reference current, and a complementary reading method of reading data by comparing currents flowing in first and second memory cells in which complementary data to be read in the memory region is stored; a register setting a security state; a mode controller setting a mode; and a control circuit controlling the reference current reading method and the complementary reading method of reading the data in the read circuit on the basis of a signal of setting a mode from the mode controller and a value of the register.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.