Abstract: A digital oscillation apparatus includes a data generator and an accumulator which function as follows. The data generator is responsive to each clock of a clock signal having a frequency fc for generating data used to generate a data string which has a total value R (R is an integer) in a repetition period of m clocks (m is an integer). Accordingly, the average value of each data of the data string generated in response to each clock becomes R/m. The accumulator has a dynamic range D (D is an integer) and is responsive to each clock of the clock signal for accumulating a sum of each data (average value=R/m) of the data string generated by the data generator and a constant A (A is an integer) until the accumulated result exceeds the dynamic range. That is, data having an average value A+R/m is accumulated in response to each clock of the clock signal.

Abstract: A liquid crystal driving system using a dynamic driving method, which includes circuits for driving liquid crystals by applying AC-converted signals containing a specific frequency which is higher than the frame-frequency and different from the duty factor of the data signals.

Abstract: In a circuit arrangement for limiting the switching-on current peaks in a switching transistor (T), for example, a switching transistor in a direct voltage converter, rectangular switching pulses of the same height (UST) are applied to the control input of the switching transistor. In order to protect, for the largest possible number of types of application, the switching transistor (T) having an equally dimensioned coil (PW) from overload, the coil is included in a branch which is common both to the control circuit and to the operating circuit of the switching transistor. For simultaneously monitoring the operating current (I) in a direct voltage converter (UB, UA), the coil is the primary coil of a current transformer (STW), whose secondary circuit includes, inter alia, the series-combination of a saturable choke (DR) and a load resistor (RB2).

Abstract: A drive circuit controls application of alternating current power to a load. The drive circuit includes an oscillator which applies a high frequency signal to a first input of a logic gate. A control signal is applied to a second input of the gate to enable the gate. A first capacitor is connected to the output of the logic gate. A rectifier connected to the first capacitor rectifies the signal from the first capacitor. A low-pass filter connected to the rectifier removes the high frequency components from the signal. A solid state switch has a switching input connected to the low-pass filter output, which switches the device into a conducting state. This circuit is particularly suited for use where many solid state switches share the same common terminal.

Abstract: In this MOS-transistor bridge circuit, for obtaining a fast flyback conduction of the current after a normal operation of the circuit, instead of the flyback diodes associated with each transistor of the bridge, the MOS transistors themselves are employed, driven so as to conduct current from the ground to the power supply, that is in the opposite direction with respect to that of normal operation. For this purpose a control section is provided receiving at the input a fast flyback signal and comprising delay gates connected to the disable inputs of the transistors, so as to delay switching off thereof, and to maintain in the on state two diagonally opposed transistors so as to allow current to flow from the ground to the power supply through these diagonally opposed transistors and the load until the current decreases to zero.

Abstract: A bridge base control circuit for a power switch. At the switching off, the base is connected with a reference terminal (M) through a first switching means (T2) having a low impedance and the emitter is connected with a supply terminal (Vcc) through a second switching means for allowing the reverse current to flow through the base-emitter junction. The second switching means has a low impedance as long as the voltage V.sub.BE is low, immediately after its switching on and that of the first switching means, and a high impedance (R1) as soon as the emitter voltage is approaching the supply voltage (VCC), this transition being automatically carried out.

Abstract: A control signal output circuit for outputting a control signal in response to first and second input signals and a power source voltage, comprises an inverter which inverts one of the first and second input signals and outputs an inverted signal. The control signal output circuit further comprises a logic circuit which outputs a control signal in response to the inverted signal and the other of the first and second input signals. A switch is further provided to disconnect the inverter from the power source voltage in response to the other of the first and second input signals.

Abstract: A system providing a drive circuit for a bipolar transistor high in speed and low in power consumption even under a low source voltage using a MOSFET is disclosed. The base current of the bipolar transistor is supplied not by short-circuiting the collector and the base thereof by a MOSFET but from another base current source.

Abstract: An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.

Abstract: Disclosed is a generator and method for using the generator to negate offset voltages in operational amplifiers. The generator includes an operational amplifier (op amp) whose input stage includes a current source coupled to a differential pair of input devices. The physical characteristics of the devices are such that an intentional offset voltage greater than the normal op amp offset voltage is provided in the input stage. The output terminal of the generator op amp is connected to the substrate terminal of one of the input devices. The offset voltages of other op amps can be negated by interconnecting the substrate terminal of one device in each input differential pair to the output terminal of the generator op amp and creating an intentional offset voltage in the input differential pair of each op amp.

Abstract: A circuit is provided for switching an internal bus of an integrated circuit between an input/output pad on the integrated circuit and a circuit node of the integrated circuit. A first switch is connected between the input/output pad and the internal bus. A second switch is connected between the circuit node and the internal bus. A high voltage detector senses the presence or absence of a voltage exceeding a preselected threshold on the input-output pad. The high voltage detector assumes a first state if the voltage on the input/output pad exceeds the preselected threshold, and assumes a second state if the voltage on the input/output pad does not exceed the preselected threshold. Switch control circuitry responsive to the high voltage detector activates either the first or second switch depending upon the output of the high voltage detector. Circuitry is provided to prevent the first and second switches from being active simultaneously and for lowering the capacitance of the input/output pad.

Abstract: A circuit for producing a reference voltage includes an NPN transistor having its emitter connected to a first terminal, its collector connected to a second terminal, a PNP transistor having its emitter connected to the second terminal, its base connected to the base of the NPN transistor, and having its collector connected to the second terminal. A current source is connected to either the first terminal or the second terminal to force a current which is divided into a current through the PNP transistor and another current through the NPN transistor. The circuit produces a reference voltage equal to the sum of the PNP V.sub.BE voltage and the NPN V.sub.BE voltage. The reference voltage tracks precisely with variations in saturation currents of the PNP transistor and the NPN transistor. The circuit is useful in producing a two V.sub.BE bias voltage between the base of an NPN pullup transistor and a PNP pulldown transistor having a common emitter connection to an output terminal.

Abstract: A high-speed swtich driver provides a precise output voltage swing for microwave switches. A first embodiment is for use with TTL circuits, and includes alternating high-gain voltage level shift and differential amplifier stages. A second embodiment also includes alternating voltage level shift and differential amplifier stages, but further has the flexibility to be used with a variety of logic circuits, including TTL, ECL, differential ECL, CMOS any circuit requiring user-defined input levels. Both embodiments provide complementary outputs at voltage levels that may be set by the user.

Abstract: A digital signal reflection attenuation device is connected to a receiving end of a transmission line and contains a reflection attenuator connected between the signal line and the ground line, and also the signal line and the supply line. The attenuator clamps the voltage of digital signals between ground potential and the supply line voltage. Thus, even with a characteristic impedance mismatch between the transmission line and the receiver, accurate digital signals can be transmitted to the receiver.

Abstract: A waveform converting apparatus includes a first and a second common-emitter type transistors as part of a first and second emitter follower circuits respectively. The follower circuits are used for converting the impedances of an input signal independently. A first constant current supply is connected to the emitter of the first transistor provided in the first emitter follower circuit, and a second constant current supply is connected to the emitter of the second transistor provided in the second emitter follower circuit. The constant current flowing in the first emitter follower circuit is adjusted to be of a smaller value than the constant current flowing in the second emitter follower circuit.

Abstract: A delay circuit for an IC device is disclosed, which comprises a charging/discharging circuit, a voltage divider and a comparator. The charging/discharging circuit selectively effects a charging/discharging operation in response to an input sigal to thereby generate a variable output voltage. The voltage divider divides a source voltage of the IC device to provide a reference voltage having a predetermined constant potential. The comparator is coupled to the charging/discharging circuit and voltage divider at its inverting input and non-inverting input, respectively, and compares the output voltage of the charging/discharging circuit with the reference voltage. A switch circuit is provided which performs a switching operation in response to the input signal to thereby electrically disconnect the non-inverting input of the comparator from the voltage divider.

Abstract: An output circuit provides both a positive and negative pulse output at a single output terminal in response to the receipt of a single trigger input pulse for triggering either negative-edge sensitive or positive-edge sensitive input stages of succeeding circuit elements. The circuit includes a latch responsive to the input trigger signal, and the output of the latch is coupled to the data input terminal of a first clocked flip-flop for setting the flip-flop upon receipt of the clock signal. The output of the first clocked fip-flop is coupled to the reset terminal of the latch to reset the output of the first clocked flip-flop to its initial state upon receipt of a second clock signal. The output circuit further includes a divide-by-2 flip-flop clocked by the opposite phase of the clock signal to provide a divided clock signal.

Abstract: A flip-flop circuit comprises two basic flip-flop circuits, four field effect transistors, and four amplifiers. The two basic flip-flop circuits respectively composed of a first and a second inverter circuits, and an output terminal of the first inverter circuit is connected to an input terminal of the second inverter circuit and an output terminal of the second inverter circuit is connected to the input terminal of the first inverter circuit. The field effect transistors have sources respectively connected to input terminals of the two basic flip-flop circuits, and gates to which clock pulses and inverse clock pulses are applied. The amplifiers respectively composed of an inverter circuit are connected to output terminals of the two basic flip-flop circuits.

Abstract: A projection type liquid crystal display device includes a light source and condenser lenses for emitting two groups of beams of light which orthogonally cross each other. A first device is disposed in the path of one of the groups of beams and comprises a liquid crystal panel and at least one polarization plate to transmit P-wave polarized light. A second device is disposed in a path of the other group of beams of light and comprises a liquid crystal panel and at least one polarization plate to transmit P-wave polarized light. A dichroic mirror disposed to receive light from the first and second devices synthesizes the P-wave polarized light by transmitting P-wave polarized light from the first device and for reflecting the P-wave polarized light from the second device.

Abstract: A gate driver circuit is provided for push-pull power transistors. Inverse square wave signals are provided to each of the driver circuits for activating the power transistors. The combination of an inductor and diodes provides a delay for activating the corresponding power transistor at a positive transition of the control signal, but do not have a significant delay at the negative transition. This provides protection to prevent the power transistors from being activated concurrently while having lower power loss at high drive frequencies. The control terminal for each power transistor is connected to a voltage clamping circuit to prevent the negative transition from exceeding a predetermined limit.