Abstract: A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and second (14) gate electrodes are arranged between the anode (10) and the cathode (16), wherein the first gate electrode (12) is an epitaxial silicon layer (20) formed upon the anode (10) and the second gate electrode (14) is an epitaxial silicon-germanium layer (24) formed upon the first gate electrode (12). The method of fabricating such a vertical thyristor comprises the steps of depositing an epitaxial silicon layer (20) upon the anode (10) and depositing an epitaxial silicon-germanium layer (24) upon the epitaxial silicon layer (20), wherein the epitaxial silicon layer (20) forms the first gate electrode (12) and the epitaxial silicon-germanium layer (24) forms the second gate electrode (14) of the vertical thyristor.

Abstract: A protected chip stack having a first chip and a second chip on the first chip. A functional layer in at least the first chip or the second chip. On the first chip and on the second chip there is in each case a connecting element, the connecting element on the first chip forming with the connecting element on the second chip a mechanical connection between the two chips. The connecting element and the functional layer are made of the same material. At least in the case of the first chip or in the case of the second chip, the connecting element is in direct contact with the functional layer.

Abstract: A MEMS microphone with a stacked PCB package is described. The MEMS package has at least one MEMS acoustic sensor device located on a PCB stack. A metal cap structure surrounds the at least one MEMS acoustic sensor device wherein an edge surface of the metal cap structure is attached and electrically connected to the PCB stack. In a first embodiment, a back chamber is formed underlying the at least one MEMS acoustic sensor device and within the PCB stack wherein an opening underlying the at least one MEMS acoustic sensor device accesses the back chamber. An opening in the metal cap structure not aligned with the at least one MEMS acoustic sensor device allows external fluid, acoustic energy or pressure to enter the at least one MEMS acoustic sensor device. In a second embodiment, a back chamber is formed in the space under the metal cap and over the first PCB.

Abstract: On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

Abstract: To provide a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time. The method of the present invention includes: forming magnetic bumps 34 on at least one of first and second bases 10A and 40 to be bonded together at their corresponding electrodes (e.g., electrodes 15 and electrodes 41); aligning the electrodes 15 of the first base 10A to positions corresponding to the electrodes 41 of the second base 40 for connection, by means of magnetic forces of the magnetic bumps 34 formed over the first base 10A; and connecting the electrodes 15 of the first base 10A to the electrodes 41 of the second base 40, wherein the alignment is made for a plurality of the first bases 10A at a time.

Abstract: A method of forming a thin film including zirconium titanium oxide including introducing a reactant including a mixture of a zirconium precursor and a titanium precursor onto a substrate, and introducing an oxidizing agent onto the substrate to form a solid material including zirconium titanium oxide on the substrate is provided. The thin film may be applied to a gate insulation layer of the gate structure, a dielectric layer of the capacitor or a flash memory device, and methods of forming the same are provided.

Abstract: An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.

Abstract: A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls.

Abstract: A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the above-described first insulating film. A mold having a pattern is imprinted on the above-described layer so as to form a second insulating film having a wiring trench and a first via, the pattern corresponding to the wiring trench and the first via. Thereafter, the above-described first insulating film is etched by using the above-described second insulating film as a mask so as to form a second via, which is connected to the first via, in the first insulating film.

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract: The present invention relates to a capacitor having a hafnium oxide and aluminum oxide alloyed dielectric layer and a method for fabricating the same. The capacitor includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer, wherein a portion of the dielectric layer contacting one of the lower electrode and the upper electrode is formed by alloying hafnium oxide and aluminum oxide together.

Abstract: A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are formed in the single-crystal Si layer. The STI regions sandwich and define a first single-crystal Si region. Next, silicon-germanium (SiGe) mixture is deposited on top of the structure in a SiGe deposition condition so as to grow (i) a second single-crystal silicon region grows up from the top surface of the first single-crystal silicon region and (ii) first and second polysilicon regions from the top surfaces of the first and second STI regions, respectively. By increasing SiGe deposition temperature and/or lowering precursor flow rate until the resulting yield is within a pre-specified range, a satisfactory SiGe deposition condition can be determined for mass production of the structure.

Abstract: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.

Abstract: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Abstract: There is provided a semiconductor device including a semiconductor circuit formed by semiconductor elements having an LDD structure which has high reproducibility, improves the stability of TFTs and provides high productivity and a method for manufacturing the same. In order to achieve the object, the design of a second mask is appropriately determined in accordance with requirements associated with the circuit configuration to make it possible to form a desired LDD region on both sides or one side of the channel formation region of a TFT.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the first mask layers are patterned to form openings exposing part of the surface of the substrate and the isolation structures. A tunneling dielectric layer and a first conductive layer are formed on the substrate. The first conductive layer is filled in the opening, and is divided into blocks by the isolation structures, the second mask layer, and the first mask layer. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the substrate to fill up the openings. Doped regions are formed in the substrate on both sides of the second conductive layer.

Abstract: Methods of assembly for a semiconductor light emitting device package may include positioning a submount on a mounting substrate with a solder material and a flux therebetween. The semiconductor light emitting device is positioned on a top side of the submount with a solder material and a flux therebetween to provide an assembled stack that has not been reflowed. The assembled stack is reflowed to attach the submount to the mounting substrate and the light emitting device to the submount.

Abstract: This invention provides methods for manufacturing compound-material wafers and methods for recycling donor substrates that results from manufacturing compound-material wafers. The provided methods includes at least one further thermal treatment step configured to at least partially reduce oxygen precipitates and/or nuclei. Reduction of oxygen precipitates and/or nuclei, improves the recycling rate of the donor substrate.