Abstract: A nonvolatile semiconductor memory on a semiconductor chip includes: a cell array region configured with a memory cell transistor having a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a floating gate electrode adjacent to the first control gate electrode; a high voltage circuit region including a high voltage transistor made of a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region; and a low voltage circuit region including a low voltage transistor made of a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and is electrically coupled with the third metallic salicide film.

Abstract: By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.

Abstract: In a semiconductor device, an insulating layer formed on a substrate and a wiring pattern layer is formed on the insulating layer. A lower mark element is defined as a groove formed in the insulating layer, and defines an overlay mark in conjunction with an upper mask element formed in a photoresist pattern coated on the insulating layer for the formation of the wiring pattern layer. The lower mark element features a width falling within a range from approximately 4 to 6 ?m, and a depth of at most 1 ?m.

Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

Abstract: The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0?x?1, 0?y?1, 0?z?1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the III-V group compound semiconductor so that only portions around points of the crystal constitute openings by using a III-V group compound semiconductor crystal having a plurality of projection shapes and a second step of growing the III-V group compound semiconductor crystal laterally by using the III-V group compound semiconductor crystal at the opening as a seed crystal. According to the present invention, an epitaxial substrate having a III-V group compound semiconductor crystal having low dislocation density and little warp is obtained.

Abstract: The present invention relates to a semiconductor substrate, a semiconductor device with high carrier mobility and a method of manufacturing the same. According to the present invention, there are provided a semiconductor substrate comprising a silicon substrate, a single crystal germanium layer formed on the silicon substrate, and a silicon layer formed on the single crystal germanium layer; a semiconductor device comprising a gate electrode formed on the semiconductor substrate, and junctions formed in the substrate at both sides of the gate electrode; and a method of manufacturing the semiconductor device. Therefore, carrier mobility of channels can be enhanced since the channels of semiconductor devices are placed within the germanium layer. Further, since the silicon layer is formed on the germanium layer, the reliable gate insulation film can be formed and a leakage current produced in a junction layer can also be reduced.

Abstract: A method for manufacturing a heat sink of a semiconductor device is described. In the method, an adhesive tape is provided, wherein the adhesive tape includes a first surface and a second surface on opposite sides, and the first surface of the adhesive tape adheres to a surface of a temporary substrate. At least one semiconductor device is provided, wherein the semiconductor device includes a first side and a second side opposite to the first side, and the first side of the one semiconductor device is pressed and set into a portion of the second surface of the adhesive tape, and the second side of the one semiconductor device is exposed. A thin metal layer is formed on the second side of the semiconductor device and the exposed portion of the second surface of the adhesive tape. A metal heat sink is formed on the thin metal layer. Then, the adhesive tape and the temporary substrate are removed.

Abstract: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the thickness of the insulating film to determine etch rates for the film at selected locations on the surface of the semiconductor wafer, and based on the determined etch rates, determining misalignment of the semiconductor wafer.

Abstract: A method of making a patterned metal oxide film includes jetting a sol-gel solution on a substrate. The sol-gel solution is dried to form a gel layer on the substrate. Portions of the gel layer are irradiated to pattern the gel layer and to form exposed portions. Irradiation causes the exposed portions of the gel layer to become at least one of substantially condensed to an oxide, substantially densified, substantially cured, and combinations thereof. The unexposed portions of the gel layer are removed, thereby forming the patterned metal oxide film.

Abstract: A method and associated structure for forming a free-standing electrostatically-doped carbon nanotube device is described. The method includes providing a carbon nanotube on a substrate in such a way as to have a free-standing portion. One way of forming a free-standing portion of the carbon nanotube is to remove a portion of the substrate. Another described way of forming a free-standing portion of the carbon nanotube is to dispose a pair of metal electrodes on a first substrate portion, removing portions of the first substrate portion adjacent to the metal electrodes, and conformally disposing a second substrate portion on the first substrate portion to form a trench.

Abstract: A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment of the present invention, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

Abstract: A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a plurality of first cylindrical semiconductor pillar regions of the first conductivity type periodically provided on a major surface of the semiconductor layer; a plurality of second cylindrical semiconductor pillar regions of a second conductivity type provided on the major surface of the semiconductor layer and being adjacent to the first semiconductor pillar regions; a plurality of first semiconductor regions of the second conductivity type provided in contact with the top of the second semiconductor pillar regions; second semiconductor regions of the first conductivity type selectively provided on the surface of the first semiconductor regions; a first main electrode provided on the first semiconductor region and the second semiconductor region; an insulating film provided on the first semiconductor pillar regions, the first semiconductor regions, and the second semiconductor regions; a control electrode provided on the

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: A plurality of element forming regions and an element isolation structural section forming region which separates the plurality of element forming regions from one another, are set to a substrate. A first thermal oxide film is formed. An HfSiON film is formed. Heating processing is done. A silicon nitride film is formed. A trench is formed which extends from an upper surface of the substrate, corresponding to the element isolation structural section forming region to within the substrate. A trench oxide film is formed. A precursor embedded oxide film is formed. The precursor embedded oxide film is removed as a height lower than the upper surface of the silicon nitride film. Then, the silicon nitride film is removed. The HfSiON film and the first thermal oxide film are removed. A second thermal oxide film is formed on an exposed surface of the substrate from which the HfSiON film and the first thermal oxide film are removed.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: An object of the present invention is to provide a nitride semiconductor based light-emitting device, which is low in operating voltage reduction and is high in performance, and a manufacturing method thereof. A first metal film is formed on a P-type conductive nitride semiconductor formed on a substrate, and then, a film (WOx) made of tungsten oxide is formed in superimposition, followed by annealing.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: An organic thin film transistor including a fluorine-based polymer thin film and method of fabricating the same. The organic thin film transistor may include a gate electrode, a gate insulating layer, an organic semiconductor layer, source electrode, and a drain electrode formed on a substrate wherein a fluorine-based polymer thin film may be formed (or deposited) at the interface between the gate insulating layer and the organic semiconductor layer. The organic thin film transistor may have higher charge carrier mobility and/or higher on/off current ratio (Ion/Ioff). In addition, a polymer organic semiconductor may be used to form the insulating layer and the organic semiconductor layer by wet processes, so the organic thin film transistor may be fabricated by simplified procedure(s) at reduced costs.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a gate insulating layer, a gate electrode, an oxide layer, and sidewalls. The gate insulating layer is formed on the substrate. The gate electrode includes an upper layer and a lower layer stacked on the gate insulating layer. The oxide layer is formed on the gate electrode. The lower layer and the upper layer can have different oxidation rates. The sidewalls are formed on the oxide layer.