Patents Examined by Tsz Chiu
  • Patent number: 9653538
    Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 16, 2017
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Frederic Boeuf, Olivier Weber
  • Patent number: 9646259
    Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 9, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
  • Patent number: 9640486
    Abstract: The invention relates to a method for marking wafers, in particular wafers for solar cell production: The method comprises the steps of manufacturing a position line (21a, 21b, 21c) on a peripheral surface of a silicon ingot or column, the ingot or column extending in an axial direction and having a longitudinal axis in the axial direction, wherein the position line extends in the axial direction along substantially the whole ingot or column and is inclined with respect to the longitudinal axis. By this position line it is possible to determine the position of a wafer cut from the ingot or column within the ingot or column, respectively. Further, an individual identification pattern (20a, 20b, 20c) of lines on the peripheral surface of the silicon ingot or column is manufactured, the individual identification pattern of lines extending in axial direction over substantially the whole ingot or column and providing an individual coding which allows to identify the silicon ingot or column.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: May 2, 2017
    Assignee: Conergy AG
    Inventors: Andre Richter, Marcel Krenzin, Jens Moecke
  • Patent number: 9627656
    Abstract: In an aspect, an organic light-emitting display apparatus is provided, including a display substrate; a sealing substrate configured to face the display substrate; a sealing material for bonding the display substrate and the sealing substrate and surrounding a circumference of the display unit; and a bonding layer comprising a plurality of through holes, wherein the plurality of through holes comprise partition walls therein.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: April 18, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Man Lee, Seung-Joon Yoo, Hyun-Soo Choi, Jae-Wook Shin
  • Patent number: 9620631
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Yuichi Oshino, Hideaki Ninomiya, Kazutoshi Nakamura
  • Patent number: 9607877
    Abstract: The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 28, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huicai Zhong, Qingqing Liang
  • Patent number: 9601672
    Abstract: Light sources are disclosed utilizing LED dies that have a light emitting surface. A patterned low refractive index layer that can support total internal reflection within the LED die is provided in optical contact with a first portion of the emitting surface. In optical contact with a second portion of the emitting surface is an input surface of an optical element. The refractive index of the low index layer is below both that of the optical element and the LED die. The optical element can have a variety of shapes and sizes.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 21, 2017
    Assignee: 3M Innovative Properties Company
    Inventors: Andrew J. Ouderkirk, Catherine A. Leatherdale, Arlie R. Conner
  • Patent number: 9564555
    Abstract: An optoelectronic semiconductor module includes a chip carrier, a light emitting semiconductor chip mounted on the chip carrier and a cover element with an at least partly light transmissive cover plate, which is arranged on the side of the semiconductor chip facing away from the chip carrier, and has a frame part, wherein the frame part laterally encloses the semiconductor chip, is joined to the cover plate in a joining-layer free fashion and is joined to the chip carrier on its side remote from the cover plate.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: February 7, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Steffen Köhler, Moritz Engl, Frank Singer, Stefan Grötsch, Thomas Zeiler, Mathias Weiss
  • Patent number: 9552997
    Abstract: Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: January 24, 2017
    Assignee: Cree, Inc.
    Inventors: Mrinal Kanti Das, Qingchun Zhang, Sei-Hyung Ryu
  • Patent number: 9536930
    Abstract: In a display device including an device substrate arranged with a plurality of pixels arranged with a light emitting device, a color filter layer with different transmission bands corresponding to each of the pixels, and a color filter substrate arranged with an overcoat layer above the color filter layer, by arranging a first light shielding layer arranged corresponding to a matrix of pixels and a second light shielding layer wider than the first light shielding layer and separated from the first light shielding layer and on a side close to a pixel, light emitted in a diagonal direction leaking to an adjacent pixel enters the second light shielding layer and by increasing the length of a light path of the incident light, the light is absorbed and attenuated by the second light shielding layer and improvements in viewing angle characteristics are achieved without decreasing the aperture ratio of a pixel.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: January 3, 2017
    Assignee: Japan Display Inc.
    Inventors: Tohru Sasaki, Toshihiro Sato, Kazuhiro Odaka
  • Patent number: 9520456
    Abstract: An organic EL display device includes: a lower electrode; an upper electrode; a first organic layer which is disposed between the lower electrode and the upper electrode and is formed of a plurality of layers including a light emitting layer formed of an organic material that emits light; a metal wire that extends between the pixels within the display region; and a second organic layer which is formed of a plurality of layers the same as that of the first organic layer and which comes into contact with a part of the metal wire and does not come into contact with the first organic layer. The upper electrode comes into contact with the metal wire in the periphery of the second organic layer. Accordingly, it is possible to uniformise the potential of the upper electrode without reducing the light emission area.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: December 13, 2016
    Assignee: Japan Display Inc.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 9502382
    Abstract: A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second side of the substrate. The coplanar waveguide transition includes a first, a second, and a third via through the substrate electrically coupling the first coplanar waveguide to the second coplanar waveguide. The coplanar waveguide transition includes voids through the substrate between the first, second, and third vias and edges of the first coplanar waveguide and edges of the second coplanar waveguide.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: November 22, 2016
    Assignee: Regents of the University of Minnesota
    Inventors: Young Seek Cho, Rhonda Rene Franklin
  • Patent number: 9490428
    Abstract: Technology capable of improving performance of a phase-change memory is provided. A recording/reproducing film contains Sn (tin), Sb (antimony), and Te (tellurium) and also contains an element X having a bonding strength with Te stronger than a bonding strength between Sn and Te and a bonding strength between Sb and Te. Here, the recording/reproducing film has a (SnXSb)Te alloy phase, and this (SnXSb)Te alloy phase includes a self-assembled superlattice structure.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: November 8, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Soeya, Toshimichi Shintani, Takahiro Odaka
  • Patent number: 9478742
    Abstract: Light emitted within an organic EL device is effectively utilized, and a pixel is provided for improving the extraction efficiency of the light. Light extraction is efficiency is improved without increasing a current by effectively utilizing guided wave light which is a cause of the loss of light emitted by an organic EL device. In order to achieve this, a stepped portion is arrange in an insulating layer provided over a lower layer of a first electrode including a light reflecting surface, and a peripheral area of the first electrode is formed so as to contact the stepped portion. The reflecting surface is formed curved towards a second electrode side in the peripheral area of the first electrode from the stepped portion, light guided through the organic EL layer is reflected by the reflecting surface and emitted from the second electrode side.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 25, 2016
    Assignee: Japan Display Inc.
    Inventors: Jun Takagi, Toshihiro Sato
  • Patent number: 9472761
    Abstract: An organic EL display device includes: a display area and an inspection area. The display area includes a plurality of first electrodes each provided in the pixel, a light-emitting organic layer formed in the light-emitting areas and formed of a plurality of organic material layers including a light-emitting layer, and a second electrode formed to cover the display area. The inspection area includes an inspection first electrode electrically formed as at least one block in the inspection area, an inspection organic layer formed of at least one organic material layer of the plurality of organic material layers and being in contact with the inspection first electrode, and an inspection second electrode formed in contact with the inspection organic layer.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 18, 2016
    Assignee: JAPAN DISPLAY INC.
    Inventors: Toshihiro Sato, Masamitsu Furuie, Naoki Uetake
  • Patent number: 9437659
    Abstract: An organic electroluminescent display device includes: a substrate; plural anodes that are formed in respective pixels; pixel separation films that cover at least an edge of the respective anodes between the respective pixels; an organic layer that covers a display area over the plurality of anodes, and the pixel separation films, and includes at least a light emitting layer; a cathode that is formed on the organic layer; and a counter substrate that is arranged on the cathode so as to face the substrate, in which the anodes each include: a contact area that comes in contact with the organic layer, and faces a corresponding pixel of the counter substrate, and a peripheral area that is formed around the contact area, and faces pixels around the corresponding pixels of the counter substrate. The organic electroluminescent display device can realize higher definition, higher luminance, and prevention of color mixture.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: September 6, 2016
    Assignee: JAPAN DISPLAY INC.
    Inventor: Toshihiro Sato
  • Patent number: 9437815
    Abstract: In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells arranged in a plurality of array blocks, where each resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction; (ii) a plurality of anode plates corresponding to the plurality of array blocks, where each resistive memory cell can include a resistive storage element having an anode coupled to one of the anode plates; (iii) an inactive ring surrounding the plurality of anode plates, where the inactive ring can include a same material as each of the plurality of anode plates; and (iv) a plurality of boundary cells located under the inactive ring.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 6, 2016
    Assignee: Adesto Technologies Corporation
    Inventor: Ming Sang Kwan
  • Patent number: 9425241
    Abstract: A display device includes a first electrode, an organic layer including a light emitting region, and a second electrode. The display device also includes a conductive layer electrically connected to the second electrode and including an opening corresponding to the light emitting region.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 23, 2016
    Assignee: Joled Inc.
    Inventors: Shigehiro Yamakita, Jiro Yamada, Takahide Ishii, Toshiaki Arai
  • Patent number: 9419245
    Abstract: In an organic EL display device configured in which an acrylic resin layer is disposed under a barrier layer that protects an OLED for flattening the barrier layer, floating the barrier layer caused by penetration of moisture into the acrylic resin can be prevented. A side surface of a bank formed in a boundary of pixels is formed into a cliff part having an inclination angle of 90° or larger in most portions of a circumstance of each pixel part, and formed into a gently sloped part having the inclination angle smaller than 90° in a part of the circumference. The electrode parts disposed within the respective pixels are connected to each other through an electrode part disposed on an upper surface of the bank, and electrode parts disposed on the gently sloped parts to form an OLED common electrode.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 16, 2016
    Assignee: JAPAN DISPLAY INC.
    Inventors: Akinori Kamiya, Toshihiro Sato
  • Patent number: 9419175
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a light emitting layer; a conductive metal layer; and a first stress application layer. The first semiconductor layer contains a nitride semiconductor crystal and receives tensile stress in a (0001) plane. The second semiconductor layer contains a nitride semiconductor crystal. The light emitting layer has an average lattice constant larger than a lattice constant of the first semiconductor layer. The conductive metal layer has a thermal expansion coefficient larger than a thermal expansion coefficient of a nitride semiconductor crystal. The first stress application layer is provided between the second semiconductor layer and the light emitting layer. The first stress application layer relaxes tensile stress applied from the metal layer to the second semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: August 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Shinji Yamada, Shinya Nunoue