Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: According to embodiments of the present invention, there are provided a thin film transistor, an array substrate and method of manufacturing the same, and a display device. The thin film transistor comprises: a gate electrode, a gate insulating layer, a semiconductor active layer, an etch stop layer, a source electrode and a drain electrode, wherein, the gate insulating layer is interposed between the gate electrode and the semiconductor active layer, the etch stop layer covers the semiconductor active layer, and has a first via hole and a second via hole formed therein which expose a part of the semiconductor active layer, the source electrode of the thin film transistor contacts with the semiconductor active layer through the first via hole, and the drain electrode of the thin film transistor contacts with the semiconductor active layer through the second via hole.

Abstract: A semiconductor device including an oxide semiconductor that is miniaturized and has favorable electrical characteristics is provided. The semiconductor device includes an oxide semiconductor film and a blocking film; a source electrode and a drain electrode electrically connected to the oxide semiconductor film; a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode; and a gate electrode in contact with the gate insulating film. The blocking film contains the same material as the oxide semiconductor film, is on the same surface as the oxide semiconductor film, and has a higher conductivity than the oxide semiconductor film.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.

Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

Abstract: A method of making a doped metal oxide comprises heating a first doped metal oxide with a laser, to form a crystallized doped metal oxide. The crystallized doped metal oxide has a different crystal structure than the first doped metal oxide.

Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.

Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

Abstract: A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.

Abstract: A semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with side surfaces of the first oxide semiconductor film, side surfaces of the second oxide semiconductor film, and the top surface of the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the top surface of the gate insulating film. A length obtained by subtracting a channel length between the source electrode and the drain electrode from a length of the second oxide semiconductor film in the channel length direction is 0.2 times to 2.0 times as long as the channel length.

Abstract: A three dimensional multilayer circuit (600) includes a plurality of crossbar arrays (512) made up of intersecting crossbar segments (410, 420) and programmable crosspoint devices (514) interposed between the intersecting crossbar segments (410, 420). Shift pins (505, 510) are used to shift connection domains (430) of the intersecting crossbar segments (410, 420) between stacked crossbar arrays (512) such that the programmable crosspoint devices (514) are uniquely addressed. The shift pins (505, 510) make electrical connections between crossbar arrays (512) by passing vertically between crossbar segments (410, 510) in the first crossbar array (512) and crossbar segments in a second crossbar array. A method for transforming multilayer circuits is also described.

Abstract: A display device includes a display area in which pixels are arranged in a matrix, and an inspection area that is formed around the display area, and has an inspection pixel, in which the display area includes plural first electrodes that are disposed in the respective pixels, a light emitting organic layer that includes plural organic material layers having a light emitting layer, and a second electrode that covers the display area, and the inspection pixel includes an inspection first electrode electrically independent from the respective first electrodes, an inspection organic layer in which at least one light emitting layer of the plural organic material layers is continuous from the display area, and comes in contact with the inspection first electrode, and an inspection second electrode that is continuous from the second electrode, and comes in contact with the inspection organic layer.

Abstract: An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, and diffusion of alkali metals from the EL element 203 formed by inkjet method into TFTs is prevented. Further, the third passivation film 45 prevents penetration of moisture and oxygen from the TFTs, and suppress degradation of the EL element 203 by dispersing the heat generated by the EL element 203.

Abstract: A semiconductor component having differently structured cell regions, and a method for producing it. For this purpose, the semiconductor component includes a semiconductor body. A first electrode on the top side of the semiconductor body is electrically connected to a first zone near the surface of the semiconductor body. A second electrode is electrically connected to a second zone of the semiconductor body. Furthermore, the semiconductor body has a drift path region, which is arranged in the semiconductor body between the first electrode and the second electrode. A cell region of the semiconductor component is subdivided into a main cell region and an auxiliary cell region, wherein the breakdown voltage of the auxiliary cells is greater than the breakdown voltage of the main cells.

Abstract: According to an embodiment, a semiconductor device includes a primary side lead, a light-emitting element electrically connected to the primary side lead, and a thyristor-type light-receiving element. The light-receiving element includes a first face for detecting light emitted from the light-emitting element, and a second face provided on an opposite side of the first face. The light-receiving element includes an anode electrode, a cathode electrode, and a gate electrode that are provided on the first face. The device further includes a secondary side first lead electrically connected to the anode electrode, a secondary side second lead electrically connected to the cathode electrode, and a secondary side third lead electrically connected to the gate electrode. The secondary side third lead is connected to the second face of the light-receiving element.

Abstract: The present invention provides a Light Emitting Diode (LED) package, comprising a Printed Circuit Board (PCB), an LED mounted on the PCB, a pillar placed higher than the LED around the LED on the PCB, a transparent plate disposed on the pillar, spaced apart from the LED, and configured to transmit light emitted from the LED, and a fluorescent layer formed on a surface of the transparent plate, facing the LED, and conformably coated with a substance for converting the light emitted from the LED into white light by changing a wavelength of the light, wherein an electrical pad of the LED and an electrical pad of the PCB are electrically connected to each other, and the LED and the fluorescent layer are spaced apart from each other.

Abstract: A thin-film LED comprising a barrier layer (3), a first mirror layer (2) succeeding the barrier layer (3), a layer stack (5) succeeding the first mirror layer (2), and at least one contact structure (6) succeeding the layer stack (5). The layer stack (5) has at least one active layer (5a) which emits electromagnetic radiation. The contact structure (6) is arranged on a radiation exit area (4) and has a contact area (7). The first mirror layer (2) has, in a region lying opposite the contact area of the contact structure (6), a cutout which is larger than the contact area (7) of the contact structure (6). The efficiency of the thin-film LED is increased as a result.

Abstract: An organic electroluminescence display device includes a thin film transistor substrate and a counter substrate, in which the thin film transistor substrate includes: a moisture blocking area that surrounds an outside of the display area and is made of only an inorganic material between the first substrate and the sealing film, and an auxiliary area between the display area and the moisture blocking area, and a thickness of areas of the counter substrate opposite to the auxiliary area and the moisture blocking area is thinner than a thickness of an area of the counter substrate opposite to the display area.

Abstract: Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes.