Abstract: A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.

Abstract: A method of joining a semiconductor die to a passive heat exchanger can include applying a bond enhancing agent to a semiconductor device; creating an assembly that includes a thermal interface disposed on the semiconductor device such that a first major surface of the thermal interface material is in touching relation with the bond enhancing agent on the semiconductor device, and a heat exchanger disposed in touching relation with a second major surface of the thermal interface material; and reflowing the assembly such that the thermal interface bonds the heat exchanger to the semiconductor device. Embodiments can use the ability of indium to bond to a non-metallic surface to form the thermal interface, which may be enhanced by a secondary coating on either or both joining surfaces.

Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.

Abstract: The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the III-V etch to stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

Abstract: The disclosed technology is directed to a method of forming a qubit device.

Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.

Abstract: A display device according to an embodiment of the present invention includes: an electrode; a light-emitting layer formed on the electrode; and a metal-containing film formed on the light-emitting layer and containing a first metallic element. The metal-containing film includes a metal layer forming an interface of the metal-containing film on the side of the light-emitting layer, formed of a simple substance of the first metallic element or an alloy of the first metallic element and a second metallic element, and a light-transmitting oxide layer forming an interface of the metal-containing film on the opposite side from the interface on the side of the light-emitting layer, formed of an oxide of the first metallic element, and having a light-transmitting property.

Abstract: A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes moisture impermeable layer. The assembly includes a first substrate and a second substrate electrically connected to a surface of the first substrate. The assembly includes a layer between the two substrates with the moisture impermeable layer between the layer and the surface of the first substrate. The layer may be non-conductive film, die attach film, capillary underfill, or the like. A portion of the surface of the first substrate may include a solder mask between the moisture impermeable layer and the first substrate. The moisture impermeable layer prevents, or at least inhibits, moisture within the first substrate from potentially creating voids in the layer. The moisture impermeably layer may be a polyimide, a polyimide-like material, an epoxy, an epoxy-acrylate, parylene, vinyltriethoxysilane, or combination thereof.

Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

Abstract: To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. By covering a side surface of an oxide semiconductor layer in which a channel is formed with an oxide semiconductor layer, diffusion of impurities into the inside from the side surface of the oxide semiconductor layer is prevented. By forming a gate electrode in a damascene process, miniaturization and high density of a transistor are achieved. By providing a protective layer covering a gate electrode over the gate electrode, the reliability of the transistor is increased.

Abstract: The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

Abstract: The present disclosure relates to a transistor device having a strained source/drain region. In some embodiments, the transistor device has a gate structure arranged over a semiconductor substrate. The transistor device also has a strained source/drain region arranged within the semiconductor substrate along a side of the gate structure. The strained source/drain region includes a first layer and a second layer over the first layer. The first layer has a strain inducing component with a first concentration profile that decreases as a distance from the second layer decreases, and the second layer has the strain inducing component with a second non-zero concentration profile that is discontinuous with the first concentration profile.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has chip and a redistribution layer. The redistribution layer is disposed on the chip. The redistribution layer includes joining portions having first pads and second pads surrounding the chip. The first pads are arranged around a location of the chip and the second pads are arranged over the location of the chip. The second pads located closer to the chip are narrower than the first pads located further away from the chip.

Abstract: A electrical switch has a first substrate, a first conducting layer disposed on the first substrate, a first dielectric layer disposed on the first conducting layer and a second conducting layer disposed on the first dielectric layer, and the second conducting layer disposed on the second substrate, and a conductive via connected to the first conducting layer and extending through the first dielectric layer. Active dielectric has a first conductor, a first dielectric layer disposed on the first conducting layer, one or more electrical switches disposed on the first dielectric layer, a dielectric layer disposed between neighboring electrical switches, the second dielectric layer disposed on the last electrical switch, and the second conducting layer disposed on the second dielectric layer.

Abstract: A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.

Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.

Abstract: A semiconductor layer sequence is disclosed. In an embodiment the semiconductor layer sequence includes an n-conducting n-region, a p-conducting p-region and an active zone having at least one quantum well located between the n-region and the p-region, wherein the semiconductor layer sequence includes AlInGaN, wherein the n-region comprises a superlattice, wherein the superlattice has a structural unit which repeats at least three times, wherein the structural unit comprises at least one AlGaN layer, at least one GaN layer and at least one InGaN layer, wherein an intermediate layer is disposed between the active zone and the superlattice, wherein the intermediate layer comprises either n-doped GaN or n-doped GaN together with n-doped InGaN so that the intermediate layer is free of aluminum, and wherein the intermediate layer directly adjoins the active zone and the superlattice.

Abstract: A light-emitting apparatus includes a plurality of packages each including a first substrate, and a single second substrate on which the plurality of packages are arrayed. The first substrate includes a first light source and a second light source. The first light source includes a first light-emitting section that emits light having a first wavelength, and first and second electrodes that are coupled to the first light-emitting section. The second light source includes a second light-emitting section that emits light having a second wavelength, and third and fourth electrodes that are coupled to the second light-emitting section. The second substrate includes first connection which is coupled to both the first electrode in a first package and the first electrode in a second package, second connection coupled to both the third electrode in the first package and the third electrode in the second package, and a driving circuit.