Abstract: Provided are a light emitting device having a nitride quantum dot and a method of manufacturing the same. The light emitting device may include: a substrate; a nitride-based buffer layer arranged on the substrate; a plurality of nanorod layers arranged on the nitride-based buffer layer in a vertical direction and spaced apart from each other; a nitride quantum dot arranged on each of the plurality of nanorod layers; and a top contact layer covering the plurality of nanorod layers and the nitride quantum dots. A pyramid-shaped material layer may be further included between each of the plurality of nanorod layers and each of the nitride quantum dots. One or the plurality of nitride quantum dots may be arranged on each of the nanorod layers.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.

Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

Abstract: An organic semiconductor crystalline film and weak oriented epitaxy growth preparation method thereof. The organic semiconductor crystalline film is a n-type semiconductor or a p-type semiconductor, and organic semiconductor crystal molecules in the organic semiconductor crystalline film are oriented in a stand-up manner on the ordered substrate, and have an oriented relationship with the ordered substrate. The organic semiconductor crystalline film prepared by the present invention is useful for organic transistor and organic phototransistor devices. The method of the present invention can control the high carrier mobility direction of organic semiconductor crystals to have ordered orientation in the film, enhance contacts between crystals, improve mechanical strength and micro-machining property of the film, and give a high carrier mobility. The carrier mobility of weak oriented epitaxially grown film of the present invention is 0.

Abstract: A device detects underfill voids and solder ball defects via laser generation and laser detection of an ultrasonic wave at the top surface of flip chips. High resolution is provided by using small laser spot sizes and closely-spaced laser beams of wavelengths that are absorbed near the surface of the semiconductor. Improved spatial resolution and rejection of unwanted scattered waves can be attained by limiting the time frame of the ultrasonic waveform to the time required for the first longitudinal wave reflection from the bottom of the flip chip. The laser beam spacing can be reduced by using probe and detection beams of different wavelengths. Resolution of less than 100 ?m features was demonstrated for silicon flip chips.

Abstract: There is provided a semiconductor device having, on a silicon substrate, a gate insulating film and a gate electrode in this order; wherein the gate insulating film comprises a nitrogen containing high-dielectric-constant insulating film which has a structure in which nitrogen is introduced into metal oxide or metal silicate; and the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film has a distribution in the direction of the film thickness; and a position at which the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film reaches the maximum in the direction of the film thickness is present in a region at a distance from the silicon substrate. A manufacturing method of a semiconductor device comprising the step of making the introduction of nitrogen by irradiating the high-dielectric-constant insulating film which is made of metal oxide or metal silicate, with a nitrogen containing plasma, is also provided.

Abstract: This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Abstract: A solid-state image capturing device includes a plurality of electrode pads for inputting and outputting a signal or voltage from and to the outside, a plurality of photoelectric conversion elements, a planarization film for planarizing the difference in the level on the surface above the plurality of photoelectric conversion elements, a microlens for focusing incident light on each of the plurality of photoelectric conversion elements, and a protection film provided above the microlens and the planarization film, the planarization film and the protection film above the plurality of electrode pads being removed as an opening, where the protection film has a protection film removing area that at least includes an area removed across all or a corner portion of the opening and the image capturing area.

Abstract: A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: An exemplary solid-state light emitting device includes a substrate, a light emitting structure, a first electrode and a second electrode have opposite polarities with each other. The light emitting structure includes a first-type semiconductor layer, a second-type semiconductor layer and an active layer between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode electrically is connected with the first-type semiconductor layer. The first electrode includes a first contact pad and a current induced electrode spaced apart and insulated from each other. The second electrode has an opposite polarity with respect to the first electrode. The second electrode includes a transparent conductive layer formed on and electrically connected with the second-type semiconductor layer and a metallic conductive layer formed on the transparent conductive layer and in electrical contact therewith.

Abstract: An illumination apparatus includes a plurality of semiconductor light-emitting devices, a reflective layer, a plurality of conductor parts and a translucent adhesive layer. Each of the semiconductor light-emitting devices has a translucent substrate, and a semiconductor light-emitting layer formed on the substrate. The reflective layer has a size on which semiconductor light-emitting devices are arranged at intervals. The conductor parts are provided on the reflective layer, and electrically connected to the semiconductor light-emitting devices. The adhesive layer bonds the substrates of the semiconductor light-emitting devices onto the reflective layer, and thereby holds the semiconductor light-emitting devices on the reflective layer.

Abstract: An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The horizontal metal lines have horizontal power metal lines and horizontal ground lines. The vertical metal lines have vertical power metal lines and vertical ground lines. The power lines and the ground lines in the horizontal metal lines are respectively interconnected with the power lines and the ground lines of the vertical metal lines. The width of the horizontal metal wires in the P/G network is such that the horizontal power metal lines only cover the power lines in the rows of the standard cells, while the horizontal ground metal lines only cover the ground lines of the rows of the standard cells.

Abstract: A main semiconductor region grown on a substrate has formed on its surface a pair of main electrodes spaced from each other, a gate electrode between the main electrodes, and a pair of diode-forming electrodes spaced farther away from the gate electrode than are the main electrodes. Making ohmic contact with the main semiconductor region, the pair of main electrodes serve both as drain or source of a HEMT switch and as cathodes of a pair of Schottky diodes integrated with the HEMT switch. Both gate electrode and diode-forming electrodes are in Schottky contact with the main semiconductor region.

Abstract: A system and method is disclosed for allowing a solid substrate, such as a printed circuit board (PCB), to act as the support structure for an electronic circuit. In one embodiment, the LEDs which form a part of a scrambler assembly are constructed on a first substrate and the electrical connections are run to the edges of the substrate and end in electrical contacts positioned thereat. The substrate is then connected to the scrambler package by a series of electrical and mechanical connections to form the LED package. The electrical contacts which are part of the LED package extend from the LED package so as to enable electrical contact with a separate controller substrate.

Abstract: A photosensor and an imaging array utilizing the same are disclosed. The photosensor includes a light conversion region that has separate charge storage regions. The light conversion region includes a plurality of separate charge storage regions within a doped region, each charge collection region being doped such that the mobile charges generated by light striking that charge storage region are prevented from moving to an adjacent charge storage region. The photosensor also includes a plurality of transfer gates, having a gate region adjacent to a corresponding one of the charge storage regions and disposed between that charge storage region and a drain region. The charge collection regions and the drain regions are doped such that the mobile charges collected in the charge storage region will flow to the drain region when a first electric field is applied to the gate region.

Abstract: A wiring line to which a high-frequency signal is applied is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an interlayer insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively and waveform rounding of an applied high-frequency signal can be reduced without increasing the number of manufacturing steps.