Patents Examined by Tu-Tu Ho
  • Semiconductor device having stable structure and method of manufacturing the same
    Patent number: 9337091
    Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 10, 2016
    Assignee: SK HYNIX INC.
    Inventor: Chan Sun Hyun
  • Semiconductor device and manufacturing method thereof
    Patent number: 9331074
    Abstract: A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and second Fin FET transistors. The first Fin FET transistor includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET transistor includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section along the second direction and across the first gate electrode, the second gate electrode and the separation plug, the separation plug has a tapered shape having a top size smaller than a bottom size.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 3, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Localized sealing of interconnect structures in small gaps
    Patent number: 9331043
    Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 3, 2016
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh, Arkalgud R. Sitaram
  • Moisture scavenging layer for thinner barrier application in beol integration
    Patent number: 9318437
    Abstract: A method of forming a thinner barrier/liner stack for vias and metal lines and the resulting device are disclosed. Embodiments include forming a via through an interlayer dielectric (ILD) and capping layer, down to a first metal layer; forming a moisture scavenging layer precursor over the ILD and on side and bottom surfaces of the via; annealing the moisture scavenging layer precursor, forming a moisture scavenging layer; forming a barrier/liner stack over the moisture scavenging layer; and depositing a second metal layer over the barrier/liner stack and filling the via and trench.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ming He, Kunaljeet Tanwar
  • Semiconductor device and fabricating method thereof
    Patent number: 9318478
    Abstract: A semiconductor device includes a first dummy gate having a first width, a second dummy gate adjacent to the first dummy gate in a lengthwise direction and having a second width, and a first bridge connecting the first dummy gate and the second dummy gate to each other. The first width and the second width are smaller than a minimum processing line width.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok-Han Bae, Dong-Kwon Kim, Jong-Hyuk Kim, Yoon-Moon Park
  • Self-aligned top contact for MRAM fabrication
    Patent number: 9318696
    Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: April 19, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yu Lu, Xia Li, Seung Hyuk Kang, Shiqun Gu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9312356
    Abstract: The semiconductor device includes a gate electrode, a first interlayer dielectric, a first mask layer, a second mask layer and a second interlayer dielectric. The first interlayer dielectric surrounds the periphery of the gate electrode, and the first mask layer is disposed on the gate electrode. The first mask layer and the gate electrode have at least one same metal component. The second mask layer is disposed on the sidewalls of the first mask layer, and the second interlayer dielectric is disposed on the second mask layer and in direct contact with the first interlayer dielectric.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Yi-Wen Chen
  • Imaging sensors
    Patent number: 9313428
    Abstract: Described herein is a pixel readout circuit which provides readout at two sensitivity levels depending on the amount of electrons generated by a pixel photodiode in the circuit. A floating diffusion capacitor operates to store charge up to a saturation value determined by its capacitance and an overflow capacitor is provided in an overflow region for storing charge above the saturation value of the floating diffusion capacitor. Readout at a high sensitivity level is provided when the floating diffusion capacitor is not saturated and readout at a lower sensitivity level is provided when there is saturation and subsequent overflow to the overflow region. Connection of the floating diffusion capacitor to the overflow capacitor shares the charge over the combined capacitance of the two capacitors and provides readout at a lower sensitivity without loss of charge.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 12, 2016
    Assignee: IMEC VZW
    Inventors: Jonathan Borremans, Koen De Munck
  • Conductive bump, semiconductor chip and stacked semiconductor package using the same
    Patent number: 9312232
    Abstract: A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: April 12, 2016
    Assignee: SK hynix Inc.
    Inventor: Hyeong Seok Choi
  • Electrode pair fabrication using directed self assembly of diblock copolymers
    Patent number: 9306164
    Abstract: Structures including alternating first U-shaped electrodes and second U-shaped electrodes and contact pads interconnecting the first and the second U-shaped electrodes are provided. Each of the first U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on one end of a substrate. Each of the second U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on an opposite end of the substrate. Every adjacent straight portions of neighboring first and second U-shaped electrodes constitute an electrode pair having a sub-lithographic pitch. Each of the contact pads overlaps and contacts the bent portion of one of the first and the U-shaped electrodes.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Michael A. Guillorn, Hiroyuki Miyazoe, Adam M. Pyzyna, Hsinyu Tsai
  • Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
    Patent number: 9305883
    Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis
  • Oxide semiconductor thin film and thin film transistor
    Patent number: 9299791
    Abstract: An oxide crystalline thin film having a comparatively high carrier mobility and suitable as TFT channel layer material is provided. The oxide semiconductor thin film of the present invention comprises an oxide that includes indium and tungsten, with the tungsten content in the W/In atomic ratio being 0.005 to 0.12, is crystalline, comprises only the In2O3 phase of bixbyite structure, and has a carrier density of 1×1018 cm?3 or less and a carrier mobility of higher than 1 cm2/Vsec. The oxide is able to include zinc further with the zinc content in the Z/In atomic ratio of 0.05 or less.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: March 29, 2016
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventor: Tokuyuki Nakayama
  • Selective gate oxide properties adjustment using fluorine
    Patent number: 9299856
    Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Byoung W. Min
  • Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same
    Patent number: 9299745
    Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xunyuan Zhang, Sean Xuan Lin, Kunaljeet Tanwar
  • CO2 sensor based on a diamond field effect transistor
    Patent number: 9291594
    Abstract: The present disclosure relates to a carbon dioxide sensor able to function in harsh environment, conditions. The carbon dioxide sensor can include a gate-less field effect transistor including a synthetic, quasi-intrinsic, hydrogen-passivated, single-crystal diamond layer exhibiting a 2-dimension hole gas effect, and a sensing layer comprising both a polymer and a hygroscopic material deposited onto a surface of the gate-less field effect transistor.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 22, 2016
    Assignee: Honeywell International Inc.
    Inventors: Mihai Brezeanu, Bogdan Catalin Serban, Octavian Buiu, Viorel Georgel Dumitru
  • Semiconductor device with a field ring edge termination structure and a separation trench arranged between different field rings
    Patent number: 9293524
    Abstract: A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 22, 2016
    Assignee: Infineon Technologies AG
    Inventors: Elmar Falck, Wolfgang Roesener, Hans Peter Felsl, Andre Stegner
  • Techniques for adhering surface mount devices to a flexible substrate
    Patent number: 9287467
    Abstract: Techniques are disclosed for attaching SMDs to a flexible substrate using conductive epoxy bond pads. Each bond pad includes a set of elongated strips of conductive epoxy that are applied and cured onto the flexible substrate in an adjacent and parallel fashion. The bond pads are used to attach SMDs to the flexible substrate and also provide the conductive contacts for a printed circuit. A circuit may be printed on the flexible substrate using conductive ink that partially covers the bond pads, leaving a portion of the pads exposed. A second layer or strip of conductive epoxy may be applied over and across the exposed portions of the bond pad strips in order to attach an SMD. The number, size, and orientation of the epoxy bond pad strips may be determined by the amount of bending the flexible substrate is expected to withstand and/or the orientation of the bend.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 15, 2016
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Richard Speer, Dave Hamby, Adam Scotch
  • Pixel array
    Patent number: 9285642
    Abstract: A pixel array includes pixel units. A gate of a sharing switch device is electrically connected to a signal line. A source of the sharing switch device is electrically connected to an active device and a sub-pixel electrode. A terminal of a first capacitance Cpp is electrically connected to the source of the sharing switch device and the sub-pixel electrode. Another terminal of the first capacitance Cpp is electrically connected to a main pixel electrode of the next pixel unit. A terminal of a second capacitance Ccc is electrically connected to a drain of the sharing switch device. Another terminal of the second capacitance Ccc is electrically connected to the main pixel electrode of the next pixel unit. 5%?(Ccc/Cpp)?25%.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 15, 2016
    Assignee: Au Optronics Corporation
    Inventors: Po-Nien Lin, Yu-Ching Wu, Tien-Lun Ting
  • Resistive random access memory and method for producing same
    Patent number: 9287501
    Abstract: A resistive random access memory includes an oxygen-poor layer disposed on a first electrode layer and formed by indium tin oxide, indium oxide, tin dioxide, or zinc oxide. An insulating layer is disposed on the oxygen-poor layer and is formed by silicon dioxide or hafnium oxide. A second electrode layer is disposed on the insulating layer. A method for producing a resistive random access memory includes preparing a first electrode layer. An oxygen-poor layer is then formed on the first electrode layer. The oxygen-poor layer is formed by indium tin oxide, indium oxide, tin dioxide, or zinc oxide. Next, an insulating layer is formed on the oxygen-poor layer. The insulating layer formed by silicon dioxide or hafnium oxide. A second electrode layer is then formed on the insulating layer.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 15, 2016
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan
  • Circuits using gate-all-around technology
    Patent number: 9281363
    Abstract: A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: March 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Hui Chen