Abstract: An integrated circuit can include a group of bond pads alternating between bond pads configured to provide a return path and bond pads configured to provide a signal bond pad. For example, five bond pads can be arranged in a return-signal-return-signal-return arrangement. The integrated circuit can further be configured to receive or transmit high frequency signals.

Abstract: A method for wafer-level packaging includes providing a semiconductor wafer having a plurality of semiconductor chips connected by connection stems in the wafer. The method further includes forming a plurality of through holes in the connections stems; forming a protective layer covering the wafer with a plurality of positions for planting soldering balls exposed. The protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers formed in the through holes. The upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers. The method also includes forming soldering balls on the positions for planting soldering balls and finally, forming a plurality of packaged individual semiconductor chip structures by cutting the wafer along the connection stems with the through holes.

Abstract: Provided is a neuromorphic device including first and second lower electrodes formed on a substrate to be electrically separated, first and second lower insulating film stacks formed at least on respective surfaces of the first and second lower electrodes, first, second, and third doped regions formed at left and right sides of the first and second lower electrodes, first and second semiconductor regions formed on the first and second lower insulating film stacks, an upper insulating film stack formed on the first and second semiconductor regions and the first, second, and third doped regions, and an upper electrode formed on the upper insulating film stack. Accordingly, a specified neuromorphic device can be reconfigured to have arbitrarily inhibitory or excitatory functionality by using the first and second lower electrodes and the lower insulating film stacks including charge storage layers formed on the surfaces of the electrodes.

Abstract: A camera module including a die having a top side and a bottom side, an image sensor is positioned on the top side of the die and a conductive via is formed through the die to provide an electrical connection between the top side and the bottom side; an overmold casing formed around the die; and a lens holder assembly attached to the top side of the die and the overmold casing. A method of producing a camera module including providing an image sensor die that is overmolded within a casing, the image sensor die having a top side and a bottom side, wherein an image sensor is positioned on the top side and a conductive via is formed through the image sensor die from the top side to the bottom side; and attaching a lens holder to the top side of the image sensor die.

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer.

Abstract: A semiconductor with reduced area is provided. A first transistor includes a first conductor, a first insulator over the first conductor, an oxide semiconductor provided over the first insulator so as to overlap with the first conductor, a second insulator over the oxide semiconductor, a second conductor over the second insulator, and a third conductor and a fourth conductor in contact with the oxide semiconductor. The oxide semiconductor includes a region overlapping with the first region and not overlapping with the second region, and a region not overlapping with the first conductor and overlapping with the second conductor in a region positioned between the third conductor and the fourth conductor when viewed from above. The second transistor is a p-channel transistor. A layer in which the first transistor is provided and a layer in which the second transistor is provided are stacked together.

Abstract: A light-emitting device comprises: a light-emitting stack comprising a first side, a second side opposite to the first side, and an upper surface between the first side and the second side; a first electrode pad formed on the upper surface; a second electrode pad formed on the upper surface, and the first electrode pad is closer to the first side than the second electrode pad; and a first extension electrode comprising a first section extended from the first electrode pad toward the second electrode pad, and a second section extended from the first electrode pad toward the first side.

Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.

Abstract: After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a handle substrate, a compound semiconductor template layer and a buried insulator layer to define a top elemental semiconductor layer portion for a p-type metal-oxide-semiconductor transistor, the second trench is vertically expanded through the buried insulator layer to provide an expanded second trench that exposes a top surface of the compound semiconductor template layer at a bottom of the expanded second trench. A stack of a compound semiconductor buffer layer and a top compound semiconductor layer is epitaxially grown on the compound semiconductor template layer within the expanded second trench for an n-type metal-oxide-semiconductor transistor.

Abstract: A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

Abstract: A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design.

Abstract: This disclosure is directed at a photoconductive element for a digital X-ray imaging system which consists of a detector element comprising a semiconducting layer for absorbing photons, an insulator layer on at least one surface of said semiconducting layer and at least two electrodes on one surface of said insulator layer; and a switching element wherein at least one layer within said switching element is in the same plane as at least one said layer within said detector element.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell region and a mark region, forming a first mask layer above the stacked layer, and forming a second mask layer above the first mask layer; forming the second mask layer into first mask pattern features and forming a first alignment mark pattern feature; forming second mask pattern features and then removing the first mask pattern features; opening part of the second mask pattern features and forming a third mask layer having an opening; removing part of the second mask pattern features; removing the third mask layer; forming a fourth mask layer; etching the first mask layer; removing the fourth mask layer and then removing the second mask pattern features; and etching the stacked layer.

Abstract: Embodiments of the disclosure generally provide multi-layer dielectric stack configurations that are resistant to plasma damage. Methods are disclosed for the deposition of thin protective low dielectric constant layers upon bulk low dielectric constant layers to create the layer stack. As a result, the dielectric constant of the multi-layer stack is unchanged during and after plasma processing.

Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.

Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.