Patents Examined by Tu-Tu Ho
  • Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements
    Patent number: 9553247
    Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: January 24, 2017
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Kazunori Oda, Masaki Yazaki
  • Solid-state image sensor and camera
    Patent number: 9548328
    Abstract: A solid-state image sensor is provided. The sensor includes a substrate having a light-receiving surface. The substrate includes a charge accumulation portion that forms part of a photoelectric conversion element, a charge holding portion arranged at a position deeper than the charge accumulation portion from the light-receiving surface, and a first transfer portion configured to transfer charges generated by the photoelectric conversion element to the charge holding portion along a depth direction of the substrate. A distance between the charge holding portion and the light-receiving surface is not less than 4 ?m.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 17, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshinori Hasegawa, Ginjiro Toyoguchi, Masahiro Kobayashi
  • IC package having non-horizontal die pad and flexible substrate therefor
    Patent number: 9548255
    Abstract: An integrated circuit (IC) package has a base, side walls mechanically connected to the base, IC dies respectively mounted on inner surfaces of the side walls or the base, and electrical connections connecting a corresponding IC die to another component of the IC package. In one embodiment, each die is electrically connected to only bond pads on its corresponding side wall or base. Each such side wall and the base have routing structures (e.g., copper traces) that connect each bond pad to another component of the IC package. The IC package is assembled using a flexible substrate that has side regions that rotate relative to the base such that the routing structures do not break. By connecting an IC die only to bond pads on its corresponding side wall or base with bond wires, the bond wires will not break during side-wall rotation.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: January 17, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: You Ge, Meng Kong Lye, Zhijie Wang
  • Hybrid exposure for semiconductor devices
    Patent number: 9543224
    Abstract: Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include encapsulating a semiconductor die with a molding compound, applying a seed layer on the die and the molding compound, applying a resist layer on the seed layer, exposing a first portion of the resist layer, and exposing a second portion of the resist layer. The first portion can include a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL. The second portion can include the second area of the resist layer that includes the electrical communications pathway.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 10, 2017
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Robert L. Sankman
  • Physical quantity sensor, pressure sensor, altimeter, electronic apparatus, and moving object
    Patent number: 9541460
    Abstract: A physical quantity sensor includes a semiconductor substrate, a diaphragm section that is disposed on the semiconductor substrate and is flexurally deformed when receiving pressure, a sensor element that is disposed on the diaphragm section, an element-periphery structure member that is disposed on one surface side of the semiconductor substrate and forms a cavity section together with the diaphragm section, and a semiconductor circuit that is provided on the same surface side as the element-periphery structure member of the semiconductor substrate.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: January 10, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Yusuke Matsuzawa
  • Reducing substrate bowing caused by high percentage sige layers
    Patent number: 9536736
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method for reducing substrate bowing resulting from the formation of strained SiGe layers having a high percentage of germanium (“high concentration SiGe”) on silicon substrates. During the epitaxial growth of the high concentration SiGe layer, carbon dopant atoms may be introduced to the crystalline lattice structure of the SiGe, forming a SiGe:C layer. The carbon dopant atoms may reduce tensile strain in the SiGe:C layer during annealing, thereby reducing substrate bowing.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana
  • Semiconductor device
    Patent number: 9530766
    Abstract: A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8). An external electrode (7) is connected in common to an emitter (E) of the transistor (2) and a cathode (K) of the temperature detection diode (4). Therefore, an external electrode for the cathode (K) of the temperature detection diode (4) can be removed, and thus the device can be reduced in size and improved in terms of ease of assembly.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: December 27, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mikio Ishihara, Kazuaki Hiyama, Tatsuya Kawase, Tsuyoshi Osaga
  • Semiconductor device and method of manufacturing the same
    Patent number: 9530735
    Abstract: A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while exposing respective ends thereof and surrounding channel layers, the stepped stack structures being separated from one another by slits, forming first and second contact plugs connected to the ends of the conductive patterns to extend along an extending direction of the channel layers, and simultaneously forming, using a spacer patterning technology (SPT), bit lines connected to one or more of the channel layers and extending along a first direction, first connecting lines extending along a second direction intersecting the first direction, and contact pads extending from the first connecting lines to be connected to the first contact plugs.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: December 27, 2016
    Assignee: SK Hynix Inc.
    Inventor: Woo Yung Jung
  • Array substrate, method for manufacturing the same, and display device
    Patent number: 9525075
    Abstract: An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: December 20, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xiang Liu
  • Electronic device and method of manufacturing semiconductor device
    Patent number: 9520572
    Abstract: There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: December 13, 2016
    Assignee: SONY CORPORATION
    Inventor: Mao Katsuhara
  • III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture
    Patent number: 9515165
    Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer and a buried layer. A gate stack is formed on each FET location. Source/drain regions are sub-etched at each said gate stack. The sub-etched source/drain regions define a channel under each said gate stack. A layered source/drain is formed in each sub-etched source/drain region.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar
  • Sensor chip
    Patent number: 9506885
    Abstract: A sensor chip comprises a substrate (1) with a front side (11) and a back side (12), and an opening (13) in the substrate (1) reaching through from its back side (12) to its front side (11). A stack (2) of dielectric and conducting layers is arranged on the front side (11) of the substrate (1), a portion of which stack (2) spans the opening (13) of the substrate (1). Contact pads (32) are arranged at the front side (11) of the substrate (1) for electrically contacting the sensor chip. A sensing element (4) is arranged on the portion of the stack (2) spanning the opening (13) on a side of the portion facing the opening (13).
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 29, 2016
    Assignee: Sensirion AG
    Inventors: Felix Mayer, Ulrich Bartsch, Martin Winger, Markus Graf, Pascal Gerner
  • High voltage depletion mode N-channel JFET
    Patent number: 9508869
    Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Stress relief MEMS structure and package
    Patent number: 9499393
    Abstract: Stress relief structures and methods that can be applied to MEMS sensors requiring a hermetic seal and that can be simply manufactured are disclosed. The system includes a sensor having a first surface and a second surface, the second surface being disposed away from the first surface, the second surface also being disposed away from a package surface and located between the first surface and the package surface, a number of support members, each support member extending from the second surface to the package surface, the support members being disposed on and operatively connected to only a portion of the second surface. The support member are configured to reduce stress produced by package-sensor interaction.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: November 22, 2016
    Assignee: MKS Instruments, Inc.
    Inventors: Lei Gu, Stephen F. Bart
  • Semiconductor device
    Patent number: 9502326
    Abstract: A semiconductor device includes a transistor, a package in which the transistor is molded, a first heatsink plate, and a second heatsink plate. The first heatsink plate is bonded to a first surface of the package, and is fixed to one surface of the transistor in the package. The second heatsink plate is bonded to a second surface of the package so as to be opposed to the first heatsink plate, and is fixed to the transistor in the package. The second surface is opposite to the first surface. A bonded surface of the first heatsink plate with the plastic body includes a high stress area in which tensile stress equal to or higher than a predetermined stress value is generated. A plurality of grooves are provided in the high stress area.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 22, 2016
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Takuya Kadoguchi
  • High frequency switching MOSFETs with low output capacitance using a depletable P-shield
    Patent number: 9502554
    Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: November 22, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Madhur Bobde, Hamza Yilmaz, Sik Lui, Daniel Ng
  • Semiconductor device
    Patent number: 9502548
    Abstract: A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a gate electrode, a field plate, a first passivation layer, and a metal layer. The active layer is disposed on the substrate. The source electrode and the drain electrode are respectively electrically connected to the active layer. The gate electrode is disposed between the source electrode and the drain electrode and above the active layer. The field plate is disposed above the active layer and between the gate electrode and the drain electrode. The first passivation layer covers the gate electrode and the field plate. The metal layer is disposed on the first passivation layer, is disposed above the gate electrode and the field plate, and is electrically connected to the source electrode.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: November 22, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Wen-Chia Liao
  • Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same
    Patent number: 9496486
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • Optoelectronic component including a conversion element and method of producing an optoelectronic component including a conversion element
    Patent number: 9490400
    Abstract: An optoelectronic component includes a layer sequence having an active layer that emits electromagnetic primary radiation during operation, at least one conversion element arranged in a beam path of the primary radiation, wherein the at least one conversion element includes converter particles and a binder material, the converter particles are distributed in the binder material, the converter particles at least partly convert the primary radiation into electromagnetic secondary radiation, and the binder material is produced from a salt of two Formulae or from a mixture of different salts of one of the two Formulae, or from a mixture of different salts of the two Formulae.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: November 8, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Sven Pihale, Florian Eder
  • Silicon carbide semiconductor device and manufacturing method of the same
    Patent number: 9490328
    Abstract: In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: November 8, 2016
    Assignee: HITACHI, LTD.
    Inventors: Naoki Tega, Keisuke Kobayashi, Koji Fujisaki, Takashi Takahama