Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

Abstract: A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of bottom-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also includes a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality pre-reserved blank regions are configured among the scan lines, the data lines and the plurality of sub-pixels; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.

Abstract: Embodiments of the invention provide an array substrate and a display device. The array substrate comprises a common electrode and a pixel electrode that are formed on a base substrate. The common electrode comprises a first common electrode and a second common electrode, the first common electrode is provided below the pixel electrode and separated from the pixel electrode by an insulating layer, the second common electrode is provided in the same layer as the pixel electrode. The pixel electrode comprises a plurality of strip electrodes, the second common electrode also comprises a plurality of strip electrodes, and the strip electrodes of the pixel electrode and the strip electrodes of the second common electrode are alternately arranged.

Abstract: A device structure including a gate structure containing a first layer of carbon nanotubes and a second layer of carbon nanotubes. The first and the second layers are stacked vertically. The first and the second layers have carbon nanotubes which have substantially homogeneous electric characteristics within each layer. The carbon nanotubes in the first layer have different electric characteristics than the carbon nanotubes in the second layer, so that the device structure exhibits a multiple threshold behavior when coupled to a voltage source. The disclosure also includes a method for fabricating a multithreshold device structure.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.

Abstract: According to one embodiment, a display device includes a first signal line, a second signal line, a first switching element, a second switching element, an insulating film, a first contact hole, a second contact hole, a first pixel electrode and a second pixel electrode. The first contact hole is formed in the insulating film, and located between the first signal line and the second signal line. The second contact hole is formed in the insulating film, located opposite to the first contact hole with respect to the second signal line, and also located side by side with the first contact hole in the first direction.

Abstract: A light-induced diode-like response in multi-layered MoSe2 field-effect transistors resulting from a difference in the size of the Schottky barriers between drain and source contacts, wherein each barrier can be modeled as a Schottky diode but with opposite senses of current rectification, wherein the diode response results from the light induced promotion of photo-generated carriers across the smaller barrier. The sense of current rectification can be controlled by the gate voltage which is able to modulate the relative amplitude between both barriers, yielding a photovoltaic response.

Abstract: A semiconductor light-emitting device includes a substrate, an LED chip mounted on the substrate, and a resin package covering the LED chip. The substrate includes a base and a wiring pattern formed on the base. The resin package includes a lens. The base includes an upper surface, a lower surface and a side surface extending between the upper surface and the lower surface. The LED chip is mounted on the upper surface of the base. The side surface of the base is oriented in a lateral direction. The wiring pattern includes a pair of first mount portions and a pair of second mount portions. The paired first mount portions are formed on the lower surface of the base. The paired second mount portions are oriented in the lateral direction and offset from the side surface of the base in the lateral direction.

Abstract: Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525° C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, which includes thereon a first region where memory elements are arranged and a second region where circuit elements driving the memory elements are arranged. The first region is provided with a stacked body including a plurality of metal films. Further, the stacked body is divided into a plurality of parts by first separation portions extending in a first direction. The second region is provided with an auxiliary pattern, which includes the stacked body together with a separation portion pair including a pair of second separation portions that divide the stacked body. The second separation portions extend in a second direction intersecting with the first direction.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.

Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).

Abstract: Embodiments generally relate to methods for forming and dismantling a hermetically sealed chamber. In one embodiment, the method comprises using room temperature laser bonding to create a hermetic seal between a first element and a second element to form a chamber. A bond interface of the hermetic seal is configured to allow the hermetic seal to be opened under controlled conditions using a release technique. In one embodiment, the chamber is formed within a microfluidic chip and the chamber is configured to hold a fluid. In one embodiment a chip comprises a first hermetic seal bonding first and second elements to create a first chamber and a second hermetic seal bonding third and fourth elements to create a second chamber encompassing the first chamber. The first hermetic seal may be broken open independently of the second hermetic seal by the application of a mechanical or thermal technique.

Abstract: A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second package has a plurality of pads connected to the pillar bump pins, respectively. A method of forming a package on package (POP) structure includes at least the following steps: providing a first package with a plurality of pillar bump pins; providing a second package with a plurality of pads; and forming the POP structure by connecting the pillar bump pins to the pads.