Patents Examined by Tuan T. Dinh
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Patent number: 11778748Abstract: A data storage device including a first printed circuit board (PCB) and a second PCB. The first PCB includes a controller, an interface configured to interface with a host device, and a first connector. The second PCB includes a non-volatile memory and a second connector. The second connector is configured to couple to the first connector to establish a communication connection between the controller and the non-volatile memory.Type: GrantFiled: February 19, 2021Date of Patent: October 3, 2023Assignee: Western Digital Technologies, Inc.Inventors: Uthayarajan A/L Rasalingam, Go Beng Siong
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Patent number: 11770899Abstract: An electronic circuit board includes a printed circuit board and first and second electronic components. The printed circuit board includes a first insulating layer, a second insulating layer attached to the first insulating layer and in which is formed an open cavity, and a second conductive layer attached to the second insulating layer. The second conductive layer is treated to form a surface solder pad. The first electronic component is housed in the open cavity of the second insulating layer. The second electronic component is placed on the second insulating layer without overlapping with the open cavity. The first electronic component and the second electronic component each include a termination soldered on the surface solder pad, the surface solder pad being shared by the first and second electronic components.Type: GrantFiled: February 25, 2020Date of Patent: September 26, 2023Assignee: SAFRAN ELECTRONICS & DEFENSEInventors: Philippe Chocteau, Denis Lecordier
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Patent number: 11770920Abstract: Disclosed is an EMI shielding material. The EMI shielding material includes a resin material and metal particles mixed with each other, and the surface of the metal particles has an insulating protective layer. Further disclosed is a communication module product, including a module element arranged on a substrate, and the periphery of the module element that requires EMI shielding is filled with said shielding material. Further disclosed is an EMI shielding process, including the following steps: a. preparing a communication module on which a module element is provided; and b. applying said shielding material to a region of the module element that needs to be EMI shielded on the communication module. The shielding material shields a chip region in a wrapping manner, that is, the shielding material wraps and shields all six surfaces or six directions of the chip, and provides shielding between chips.Type: GrantFiled: September 11, 2020Date of Patent: September 26, 2023Assignee: HUZHOU JIANWENLU TECHNOLOGY CO., LTD.Inventors: Linping Li, Jinghao Sheng, Zhou Jiang
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Patent number: 11769429Abstract: A magnetic erasing device including a magnet that includes an S pole and an N pole extending along an axial direction of the magnet, and a rotation mechanism for rotating the magnet in a housing around an axis of the magnet, wherein lines of magnetic force generated around the axis of the magnet during rotation of the magnet are designed to be applied to magnetic particles in the microcapsules to erase a visible image on a magnetic panel when the axis of the magnet is spaced from a surface of the magnetic panel by a predetermined distance.Type: GrantFiled: March 31, 2021Date of Patent: September 26, 2023Assignee: Zero Lab Co., Ltd.Inventor: Ritsuo Koga
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Patent number: 11765815Abstract: A bi-directional solid state switch includes: a first bus bar; a second bus bar; a first solid state switch implemented on a first printed circuit board (PCB), the first solid state switch including: a first control terminal; a first terminal electrically connected to the first bus bar; and a second terminal; and a second solid state switch implemented on a second PCB, the second solid state switch including: a second control terminal; a third terminal electrically connected to the second terminal of the first solid state switch; and a fourth terminal electrically connected to the second bus bar.Type: GrantFiled: December 23, 2020Date of Patent: September 19, 2023Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Rashmi Prasad, Chandra S. Namuduri, Muhammad H. Alvi
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Patent number: 11756857Abstract: An electronic circuit has three circuit carriers and two semiconductor components. A first semiconductor component contacts with its upper side an underside of a first circuit carrier, and with its underside an upper side of a second circuit carrier. The first circuit carrier has vias, with a first via connecting the first semiconductor component to a first conducting path and a second via connecting a connection element forming a second conducting path providing an integral connection between the circuit carriers. A second semiconductor component contacts the underside of the first circuit carrier and is electrically connected to the first or second conducting path. An underside of the second semiconductor component contacts an upper side of the third circuit carrier. A lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of both the second and the third circuit carrier.Type: GrantFiled: June 5, 2020Date of Patent: September 12, 2023Assignee: Siemens AktiengesellschaftInventors: Thomas Bigl, Alexander Hensler, Stephan Neugebauer, Stefan Pfefferlein
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Patent number: 11751353Abstract: A power conversion module and method of forming the same includes a motherboard having a first surface and a second surface that opposes the first surface. The motherboard includes a first trace that electrically couples a decoupling capacitor mounted on the motherboard to a first pad on the first surface of the motherboard and an output node of a power conversion module. The motherboard includes a via extending through the motherboard that electrically couples a second pad on the first surface of the motherboard and a third pad on the second surface of the motherboard to the output node and a second trace that electrically couples a fourth pad on the second surface of the motherboard and the decoupling capacitor. The power module includes a first daughterboard mounted on the first surface of the motherboard and a second daughterboard mounted on the second surface of the motherboard.Type: GrantFiled: May 12, 2021Date of Patent: September 5, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Vivek Kishorechand Arora, David Ryan Huitink, Hayden Seth Carlton, Fang Luo, Asif Imran Emon
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Patent number: 11744005Abstract: An electronic component module includes a board, an electronic component, a sealing portion, a metal layer, and a magnetic layer. The board has a first main surface. The electronic component is provided on a first main surface of the board. The sealing portion seals the electronic component. The metal layer covers the sealing portion. The magnetic layer is provided between the sealing portion and the metal layer. The magnetic layer has a magnetic main body and a first cover sheet. The first cover sheet is provided between the magnetic main body and the metal layer. The first cover sheet has a first main surface and a second main surface. The first main surface faces the magnetic main body. The second main surface faces the metal layer. The second outer peripheral end of the second main surface is located inside the first outer peripheral end of the first main surface.Type: GrantFiled: April 22, 2021Date of Patent: August 29, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Hideki Shinkai
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Patent number: 11744018Abstract: Provided is a high-density multi-component package comprising a first module interconnect pad and a second module interconnect pad. At least two electronic components are mounted to and between the first module interconnect pad and the second module interconnect pad wherein a first electronic component is vertically oriented relative to the first module interconnect pad. A second electronic component is vertically oriented relative to the second module interconnect pad.Type: GrantFiled: January 13, 2021Date of Patent: August 29, 2023Assignee: KEMET Electronics CorporationInventors: John Bultitude, Peter Alexandre Blais, James A. Burk, Galen W. Miller, Hunter Hayes, Allen Templeton, Lonnie G. Jones, Mark R. Laps
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Patent number: 11737219Abstract: A power adapter includes a first output port, a second output port, a motherboard, a first flyback power module, a second flyback power module, a bus capacitor and an EMI module. The first flyback power module has a first circuit board and is electrically connected to the first output port. The second flyback power module has a second circuit board and is electrically connected to the second output port. The EMI module has a third circuit board and is arranged on the motherboard. The first circuit board and the second circuit board are arranged in parallel with each other, and are arranged substantially perpendicular to the motherboard on a first side of the motherboard.Type: GrantFiled: March 30, 2021Date of Patent: August 22, 2023Assignee: Delta Electronics (Shanghai) CO., LTDInventors: Haibin Song, Jian Zhou, Daofei Xu, Jinfa Zhang
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Patent number: 11726373Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.Type: GrantFiled: October 24, 2022Date of Patent: August 15, 2023Inventors: Hajime Kimura, Shunpei Yamazaki
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Patent number: 11721633Abstract: A circuit pattern, which is a second negative electrode wiring, and a horizontally extending area of a circuit pattern, which is a first negative electrode wiring, are connected electrically and mechanically by a vertically extending area of the circuit pattern and wires, which are an inter-negative-electrode wiring. As a result, N terminals and N1 terminals are equal in potential in a semiconductor device. The N terminals of a converter circuit section and the N1 terminals of an inverter circuit section are electrically connected to make the N terminals and the N1 terminals equal in potential.Type: GrantFiled: October 29, 2021Date of Patent: August 8, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masaki Takahashi, Kousuke Komatsu, Rikihiro Maruyama
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Patent number: 11723150Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.Type: GrantFiled: September 4, 2020Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
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Patent number: 11711889Abstract: A shield case, joined to a circuit board on which electronic components are mounted and covering the electronic components, has a top plate portion covering the electronic components, and a plurality of terminal leg portions formed in a way of projecting in a direction intersecting with the top plate portion from a peripheral edge portion of the top plate portion. Each of the plurality of terminal leg portions has: a leg portion stretching from the top plate portion; a terminal portion which extends in a direction intersecting with the leg portion from a front-end of the leg portion and is joined to the circuit board; and an expansion terminal portion which is formed by bending a front-end portion of each of the terminal portions along an end surface of the circuit board and has a length exceeding a thickness of the circuit board.Type: GrantFiled: March 24, 2021Date of Patent: July 25, 2023Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Mitsuhiro Nakamura
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Patent number: 11705442Abstract: According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.Type: GrantFiled: March 3, 2021Date of Patent: July 18, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Atsushi Hosokawa, Yasuhisa Shintoku, Yasukazu Noine, Yoshiharu Katayama
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Patent number: 11703252Abstract: An antistatic structure includes a casing, an element disposed in the casing, and a first conductive member disposed on an inner face of the casing and configured to send static electricity to a ground. The first conductive member is at least partially disposed around a region opposite the element in the casing.Type: GrantFiled: June 21, 2022Date of Patent: July 18, 2023Assignee: Daikin Industries, Ltd.Inventor: Takayuki Hattori
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Patent number: 11682660Abstract: The present disclosure provides a semiconductor structure including a first substrate having a first surface, a first semiconductor device package disposed on the first surface of the first substrate, and a second semiconductor device package disposed on the first surface of the first substrate. The first semiconductor device package and the second semiconductor device package have a first signal transmission path through the first substrate and a second signal transmission path insulated from the first substrate. The present disclosure also provides an electronic device.Type: GrantFiled: October 21, 2020Date of Patent: June 20, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuanhao Yu, Chun Chen Chen, Shang Chien Chen
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Patent number: 11676758Abstract: A magnetic device comprising a magnetic body, a coil disposed in the magnetic body and at least one thermal conductive layer, wherein a first portion of the at least one thermal conductive layer encapsulates at least one portion of the coil and a second portion of the at least one thermal conductive layer is exposed from the magnetic body, wherein the at least one thermal conductive layer forms a continuous thermal conductive path from the coil to the outside of the magnetic body for dissipating heat generated from the coil.Type: GrantFiled: March 17, 2020Date of Patent: June 13, 2023Assignee: CYNTEC CO., LTD.Inventors: Wenyu Lin, TsungHao Lu, Hao Chun Chang
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Patent number: 11678437Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal be is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.Type: GrantFiled: March 24, 2021Date of Patent: June 13, 2023Inventors: Jong-Hyun Seok, Gyu Chae Lee, Jeong Hyeon Cho
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Patent number: 11668984Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals in the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.Type: GrantFiled: April 7, 2022Date of Patent: June 6, 2023Assignee: Japan Display Inc.Inventors: Hideaki Abe, Yasuhito Aruga, Hiroyuki Onodera, Hiroki Kato, Yasushi Nakano, Hitoshi Kawaguchi, Keisuke Asada