Abstract: An electrically programmable fuse includes a first contact, a second contact spaced from the first contact, and a link between and electrically connecting the first contact and the second contact. The first contact, the second contact and the link include semiconductor material. A gate structure is partially over the link, leaving an uncovered link region uncovered by the gate structure. A silicide region is within the uncovered link region and provides an effective fuse link. The gate structure blocks silicide formation over an entirety of the fuse link, reducing the width of the effective fuse link, reducing the necessary programming current and the overall size of the electrically programmable fuse.

Abstract: The invention provides a display device and a display panel. The display device includes the display panel and a reading circuit. The display panel includes an upper substrate, a lower substrate, a thin-film transistor (TFT) layer, and a photosensitive circuit. The TFT layer is disposed between the upper substrate and the lower substrate. A plurality of TFTs of a pixel array of the display panel are disposed in the TFT layer. The photosensitive circuit is disposed in the TFT layer to sense an ambient light. The reading circuit is coupled to the photosensitive circuit to read a sensing result.

Abstract: A solid state image sensor according to an embodiment includes a transfer gate, a floating diffusion portion that converts signal charge transferred from a photodiode via the transfer gate into a voltage signal, and an extraction electrode that is formed of a film of conductive material including any of amorphous silicon, monocrystalline silicon, or N+ polysilicon, that has a peripheral edge portion surrounded by a film of insulating material and one end electrically connected to the floating diffusion portion, and that transmits the voltage signal.

Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.

Abstract: A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.

Abstract: The present application discloses a double-layer stacked CMOS image sensor, photo diode and transfer gate transistor of a pixel cell are formed on the first substrate sequentially along a longitudinal direction, and the other pixel transistors of the pixel cell are formed on the second substrate. The first substrate and the second substrate are packaged separately, and the second substrate is stacked on the top side of the first substrate instead of being in juxtaposition. Since the photo diode and the pixel transistors other than the transfer gate transistor of the pixel cell are located on two separate substrates respectively, the area of a photo diode region may be increased significantly, thereby greatly increasing full well capacitance of the image sensor and increasing a dynamic range, and reduce a dark current and image noise significantly, thereby improving the dark line noise and full well capacitance simultaneously.

Abstract: A device wafer processing method includes a protective film forming step of forming a protective film that covers a face side of a device wafer, a mask forming step of, after the protective film forming step is carried out, applying a laser beam along streets and forming, in the protective film, a mask that has grooves extending along the streets, a device layer plasma etching step of, after the mask forming step is carried out, performing plasma etching on a device layer of the device wafer by device layer gas through the mask, and a base member plasma etching step of, after the device layer plasma etching step is carried out, performing plasma etching on the base member by base member gas through the mask.

Abstract: Embodiments of present invention provide a method. The method includes forming a set of metal pillars on a substrate; forming a negative-tone organic dielectric layer covering the set of metal pillars; planarizing the negative-tone organic dielectric layer to expose the set of metal pillars; forming a resist mask on the negative-tone organic dielectric layer, the resist mask having openings that expose the set of metal pillars; and forming a redistribution layer in the openings of the resist mask, the redistribution layer being in direct contact with the set of metal pillars. A structure formed thereby is also provided.

Abstract: In a photoelectric conversion device, a first photoelectric conversion unit and a second photoelectric conversion unit are arranged so as to be aligned in a first direction in a plan view with respect to a substrate, the sensitivity of a third photoelectric conversion unit is lower than the sensitivity of the first photoelectric conversion unit and lower than the sensitivity of the second photoelectric conversion unit, and the third photoelectric conversion unit is arranged along a part of the outer circumference of a region including the first photoelectric conversion unit and the second photoelectric conversion unit in the plan view.

Abstract: A semiconductor device includes semiconductor elements arranged in a first direction, an arm connection portion disposed between the semiconductor elements in the first direction, first and second power supply terminals disposed on the same side in the first direction, first and second substrates interposing the semiconductor elements therebetween, and a sealing body. The second substrate includes an insulating base member, a front-face metal body and a back-face metal body. The front-face metal body includes a second power supply wiring and a second relay wiring. The second power supply wiring includes a base portion on which the second element is arranged, and a pair of extending portions extending from the base portion in the first direction. The second relay wiring is disposed between the extending portions in a second direction, so that the second relay wiring and the base portion satisfy a relationship of L1<L2<L3.

Abstract: A method of manufacturing a high-frequency device includes mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer covering the first chip on the metal base, exposing an upper surface of the first pillar from the insulator layer, and forming a first wiring connected to the first pillar on the insulator layer and transmitting a high-frequency signal.

Abstract: Some embodiments relate to an integrated chip including a bottom electrode over a semiconductor substrate. A seed layer overlies the bottom electrode. A data storage structure is arranged on the seed layer. A first buffer layer is arranged between the bottom electrode and the seed layer. The first buffer layer is in physical contact with the seed layer and opposing sidewalls of the first buffer layer are aligned with opposing sidewalls of the seed layer.

Abstract: An apparatus is described having: a baseplate; an AC busbar mounted on the baseplate; a DC busbar having an upper DC busbar, a lower DC busbar and an insulating material therebetween, wherein the DC busbar is mounted such that the lower DC busbar is mounted to the baseplate and wherein the upper DC busbar has one or more openings through which the lower DC busbar is exposed; a first group of switching components mounted on the AC busbar, wherein the first group of switching components are connected to the upper DC busbar using first electrical connection means; and a second group of switching components mounted on the lower DC busbar, wherein at least one of the switching components of said second group of switching components is mounted within one of said openings, wherein the second group of switching components are to the AC busbar using second electrical connection means.

Abstract: An integrated sensor array device and method. The method includes providing a partially completed semiconductor substrate having a material stack used to form a sensor array device with a plurality of device regions. One or more isolation trench regions separating the device regions can be formed in a front-end isolation process during the formation of the device regions or in a back-end isolation process following a bonding process to integrate the sensor array device to an integrated circuit (IC) device. Prior to the front-end or back-end processing, metal interconnect materials within a passivation material can be formed via a planarization process to provide connection to n-type and p-type contact regions of the sensor array device. The resulting planarized sensor array device can then be bonded to the IC device, and a plurality of surface relief structures can be formed overlying a backside surface region of the planarized sensor array device.

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of insulating layers and a plurality of gate lines configured to be alternately stacked, and a cell plug configured to pass through the plurality of insulating layers and the plurality of gate lines, wherein the plurality of gate lines, each made of a conductive material, are etched together with the plurality of insulating layers, and the cell plug includes a blocking layer, a charge trap layer, a tunnel insulating layer, a channel layer, and a core pillar.

Abstract: Provided is a solid-state imaging element with which it is possible to minimize crosstalk between different pixel columns while suppressing a decrease in quantum efficiency of a photoelectric conversion unit due to a pixel separating section. The solid-state imaging element includes a plurality of pixels arranged in a two-dimensional matrix in the X direction and the Y direction and including a photoelectric conversion unit (N-type semiconductor thin film) containing a compound semiconductor. In addition, the solid-state imaging element includes a pixel separating section disposed only at a pixel boundary extending in the X direction.

Abstract: Various embodiments of the present application are directed toward an integrated chip (IC). The IC comprises a dielectric structure disposed over a substrate. A phase change material (PCM) structure is disposed over the dielectric structure. A first conductive structure and a second conductive structure are disposed over and electrically coupled to the PCM structure. A heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. The heating structure has a first surface and a second surface opposite the first surface. The first surface faces the PCM structure. The first surface has a first width and the second surface has a second width that is greater than the first width.

Abstract: An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.

Abstract: A semiconductor device includes: a first semiconductor structure including a stacked structure of a first dielectric layer and a first bonding dielectric layer; a second semiconductor structure including a stacked structure of a second dielectric layer and a second bonding dielectric layer; and a bonding pad penetrating the stacked structure of the first dielectric layer and the first bonding dielectric layer, and the stacked structure of the second dielectric layer and the second bonding dielectric layer, wherein the first bonding dielectric layer and the second bonding dielectric layer contact each other, and a first width of a first portion of the bonding pad penetrating the first dielectric layer is greater than each of a second width of a second portion of the bonding pad penetrating the first bonding dielectric layer, and a third width of a third portion of the bonding pad penetrating the second bonding dielectric layer.