Abstract: The image sensing structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes at least one first unit. The at least one first unit includes a plurality of first interconnects adjacent to the top side of the first semiconductor device, a row selector, and an analog-to-digital converter (ADC) connected to the row selectors. The second semiconductor device includes at least one second unit. The at least one second unit includes a photodiode facing the top side of the second semiconductor device. The photodiode is configured to receive the light incident on the top side of the second semiconductor device. The top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device.

Abstract: A display device includes a substrate; a first active layer disposed on the substrate; and a first gate electrode overlapping a part of the first active layer, the first gate electrode having a hole, and the hole of the first gate electrode does not overlap the first active layer.

Abstract: In various aspects, a device-to-device communication system is provided including a first device and a second device. Each of the first device and the second device includes an antenna, a radio frequency frond-end circuit, and a baseband circuit. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a cover structure housing the first device and the second device. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a radio frequency signal interface wirelessly communicatively coupling the first device and the second device. The radio frequency signal interface includes the first antenna and the second antenna.

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a first bit line on a center region of the memory cell region, a first landing pad on the first bit line, a first bit line capping pattern between the first bit line and first landing pad, a second bit line on an edge region of the memory cell region, a second landing pad on the second bit line, and a second bit line capping pattern between the second bit line and the second landing pad. The first and second bit line capping patterns vertically overlap the first and second landing pads, respectively. A distance from the top of the first bit line capping pattern from the top of the first landing pad is greater than a distance from the top of the second bit line capping pattern to from the top of the second landing pad.

Abstract: A light emitting diode (LED) device is provided, comprising: a circuit board; a plurality of LED packages arranged on the circuit board, an LED package comprising: a pair of red LEDs arranged adjacent to one another, the pair of red LEDs configured to emit respective red light at respective different red wavelengths; a pair of green LEDs arranged adjacent to one another, the pair of green LEDs configured to emit respective green light at respective different green wavelengths; a pair of blue LEDs arranged adjacent to one another, the pair of blue LEDs configured to emit respective blue light at respective different blue wavelengths. The LED device further comprises an integrated circuit (IC) configured to independently control the pair of red LEDs, the pair of green LEDs and the pair of blue LEDs; and an electrical connector connected to respective integrated circuits of the plurality of LED packages.

Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes a base; a buffer layer and a thin film transistor. The buffer layer is provided on the base and includes a first buffer layer and a second buffer layer. The first buffer layer is disposed between the second buffer layer and the base. A refractive index of the first buffer layer is greater than a refractive index of the base and a refractive index of the second buffer layer. A ratio of the refractive index of the first buffer layer to the refractive index of the base is less than or equal to 1.25. The thin film transistor is provided on a side of the buffer layer away from the base.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-PD layout for enhanced scaling down. The pixel spans a first integrated circuit (IC) die and a second IC die stacked with the first IC die. The pixel comprises a plurality of photodetectors in the first IC die, and further comprises a plurality of pixel transistors split amongst the first IC die and the second IC die. The plurality of photodetectors are grouped into one or more pairs, each having the dual-PD layout. A DTI structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. As such, the DTI structure completely separates the plurality of photodetectors from each other.

Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface, and a pixel separation part in the substrate, the pixel separation part separating a plurality of pixels from each other, the plurality of pixels including first to fourth pixels in a clockwise direction, the pixel separation part including a first part between the first and second pixels, and a second part between the first pixel and the third pixel. Each of the first part and the second part includes a first dielectric pattern covering a lateral surface of the substrate, and a first silicon pattern covering a lateral surface of the first dielectric pattern. The second part further includes a second silicon pattern adjacent to a sidewall of the first silicon pattern. The second silicon pattern has a rhombic shape in a plan view.

Abstract: The present disclosure provides a display substrate and a display apparatus. The display substrate includes a base substrate, including a display region and a frame region located on at least one side of the display region; a transistor, located on the base substrate, wherein the transistor is located in the display region and includes a gate, a first electrode and an active layer; and a protective structure, located on the base substrate, wherein the protective structure is provided in the frame region and close to the display region, and the protective structure is in the same layer as and is made of the same material as at least one of the active layer, the gate or the first electrode.

Abstract: The application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and multiple Word Lines (WLs), the multiple WLs extend along a first direction and are arranged on the substrate at intervals along a second direction, a WL isolation structure is arranged between every two adjacent WLs and includes at least a first isolation layer and a second isolation layer stacked along the second direction and made of different materials, and the first direction and the second direction intersect with each other.

Abstract: A semiconductor device may include: a first access line extending in a first direction; a second access line extending in a second direction intersecting the first direction; and a memory cell connected between the first access line and the second access line and including an electrode including a dielectric barrier therein.

Abstract: An imaging element includes plural pixels in each of which a photoelectric conversion unit and a charge holding unit that holds charges transferred from the photoelectric conversion unit are arranged in a first direction, the plural pixels include a first pixel, in the photoelectric conversion unit of the first pixel, a light-receiving region and a light shielding region are arranged in a second direction intersecting with the first direction, and a width of the photoelectric conversion unit in the second direction is larger than a width of the charge holding unit in the second direction.

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

Abstract: A ferroelectric memory device includes a substrate, a gate structure disposed over the substrate. The gate structure includes a plurality of gate electrode layers spaced apart from each other along a first direction substantially perpendicular to a surface of the substrate. The ferroelectric memory device includes a first electrode pillar and a second electrode pillar that extend along the first direction and are disposed to be spaced apart from each other in a second direction substantially parallel to the surface of the substrate inside a hole penetrating the gate structure, and a device isolation structure disposed to cross the first and second electrode pillars and to separate the gate structure over the substrate. The gate structure further includes a plurality of ferroelectric layers and a plurality of channel layers which are disposed to correspond to the plurality of gate electrode layers.

Abstract: A semiconductor device includes: a plurality of word line pad portions that are stacked over a lower structure in a direction perpendicular to a surface of the lower structure; horizontal-level dielectric layers between the word line pad portions; and bridge prevention layers disposed between the word line pad portions and covering ends of the horizontal-level dielectric layers.

Abstract: A photoelectric conversion device including pixels arranged in a semiconductor layer including first and second main surfaces is provided. Each of the pixels includes a first photodiode including a first region of a first conductivity type where signal charges are accumulated, a second photodiode arranged between the first region and the second main surface so as to at least partially overlap the first region, and including a second region of the first conductivity type where signal charges are accumulated, a third region of a second conductivity type arranged between the first and second region, and a first electrode arranged on the first main surface so as to cover the first region. Signal charges accumulated in the second region are transferred to the first region via a transfer portion formed in the third region by controlling a potential of the first electrode.

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same, and an object thereof is to provide a semiconductor and a method for manufacturing the same, the semiconductor device not diffusing a material of a metal layer to a semiconductor substrate. A semiconductor device of the present disclosure includes a semiconductor substrate which is formed of GaAs, a first barrier layer which is formed of an alloy containing Ni on the semiconductor substrate, a second barrier layer which is formed of Co or an alloy containing Co on the first barrier layer, and a metal layer which is formed on the second barrier layer. A Ni concentration in the first barrier layer is 80 at % or lower.

Abstract: Provided is an image sensor, which includes a first substrate that has a first surface and a second surface opposite to the first surface, and includes a pixel array area and an edge area, the edge area including a first conductive pad; an anti-reflection structure on the second surface; a pixel isolator in the first substrate and defining and separating pixels; and a micro lens array that is disposed on the anti-reflection structure, in which the anti-reflection structure includes a first insulating layer, a conductive layer, a second insulating layer, and a third insulating layer sequentially stacked, the conductive layer is on the pixel array area, and is not at least in a portion of the edge area where the first conductive pad is arranged, and a voltage is configured to be applied to the conductive layer.

Abstract: An imaging element according to the present disclosure includes a pixel, an overflow path, a pixel isolation unit, a pixel isolation electrode, an in-pixel isolation unit, and an in-pixel isolation electrode. The pixel includes a plurality of photoelectric conversion units formed in a semiconductor substrate having an interconnect region arranged on a front surface side and performs photoelectric conversion of incident light. The overflow path mutually transfers charges between the plurality of photoelectric conversion units. The pixel isolation unit is at a boundary of the pixel. The pixel isolation electrode is in the pixel isolation unit, and a first bias voltage is applied to the pixel isolation electrode. The in-pixel isolation unit isolates the plurality of photoelectric conversion units from each other. The in-pixel isolation electrode is arranged in the in-pixel isolation unit, and a second bias voltage is applied to the in-pixel isolation electrode.

Abstract: An electrically programmable fuse includes a first contact, a second contact spaced from the first contact, and a link between and electrically connecting the first contact and the second contact. The first contact, the second contact and the link include semiconductor material. A gate structure is partially over the link, leaving an uncovered link region uncovered by the gate structure. A silicide region is within the uncovered link region and provides an effective fuse link. The gate structure blocks silicide formation over an entirety of the fuse link, reducing the width of the effective fuse link, reducing the necessary programming current and the overall size of the electrically programmable fuse.