Abstract: An image sensor device includes nanostructures for improving light absorption efficiency. The image sensor device includes a substrate, a light absorption region, and a nanostructure array. The light absorption region is over the substrate. The nanostructure array us over the light absorption region. The nanostructure array includes a plurality of nanostructures repeatedly arranged from a top view.

Abstract: In a semiconductor device, a semiconductor substrate has an IGBT region and a FWD, and includes a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region. The collector layer includes an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer. Alternatively, the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer, and has an area density of 3.5×1012 cm?2 or less.

Abstract: A passive component includes a substrate having insulating properties and having a surface having a recess, a bottom electrode filling at least a portion of the recess, a dielectric film provided on a surface of the bottom electrode, and a top electrode opposite to the bottom electrode with the dielectric film interposed therebetween. In a height direction perpendicular to the surface of the substrate, a dimension of the bottom electrode is larger than a dimension of the dielectric film.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a first insulation layer. The first insulation layer includes a plurality of first openings, the first opening is configured to expose a first electrode to form an effective light emitting region, at least one effective light emitting region at least partially surrounds at least one island region; a second insulation pattern, the first electrode, a first insulation pattern of the first insulation layer, a light emitting layer and a second electrode are sequentially provided in the island region along a direction facing away from the base substrate, a distance between a portion of the first electrode in the island region and a main surface of the base substrate is greater than a distance between a portion of the first electrode in the effective light emitting region and the main surface of the base substrate.

Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.

Abstract: Characteristics of a semiconductor device having a non-volatile memory are improved. The non-volatile memory has the following configuration: a semiconductor substrate; a first gate electrode portion arranged over the semiconductor substrate; a second gate electrode portion arranged over the semiconductor substrate so as to be adjacent to the first gate electrode portion; a first insulating film formed between the first gate electrode portion and the semiconductor substrate; a second insulating film formed between the second gate electrode portion and the semiconductor substrate and having a charge storage portion therein; and a first side wall insulating film arranged on a side surface side of the second gate electrode portion opposite to the first gate electrode portion, the charge storage portion being made of a high dielectric constant film containing hafnium and oxygen, and a gap being provided between the first side wall insulating film and the charge storage portion.

Abstract: A method of producing a semiconductor device includes providing a semiconductor die, providing a metal joining partner, forming a diffusion solderable region by an inkjet metal printing process, forming an assembly to include the diffusion solderable region in between the metal joining partner and the semiconductor die, and performing a diffusion soldering process that forms a soldered joint from the diffusion solderable region in between the semiconductor die and the metal joining partner.

Abstract: An image sensor includes a semiconductor layer including a first section and a second section, the semiconductor layer having a first surface and a second surface that face each other, a device isolation layer in the semiconductor layer and defining a plurality of pixels; a first grid pattern on the first surface of the semiconductor layer over the first section; and a light-shield pattern on the first surface of the semiconductor layer over the second section. A top surface of the first grid pattern is located at a first level, a top surface of the light-shield pattern is located at a second level, the first level is lower than the second level, and the first and second levels are defined with respect to the first surface of the semiconductor layer.

Abstract: There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.

Abstract: A magnetoresistive element of the present disclosure includes a multilayer structure made up of at least a fixed magnetization layer, an intermediate layer and a storage layer. A first side wall is formed on a side wall of the multilayer structure. A second side wall is formed on the first side wall. The first side wall is made of an insulating material, for instance SiN or AlOx, that prevents intrusion of hydrogen. The second side wall is made of a hydrogen storage material, for instance titanium.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps.

Abstract: A quantum gate device includes a first superconducting circuit which includes at least one of Josephson devices in an annular circuit including a superconducting wire and resonates at a first resonance frequency, a second superconducting circuit which includes at least one of Josephson devices in an annular circuit including a superconducting wire and resonates at a second resonance frequency, a connection unit which includes a capacitor and a superconducting wire provided at each electrode of the capacitor and connects the first and second circuits, a magnetic field application means applying a magnetic field to one or both of the first and second circuits, a quantum gate control electromagnetic wave irradiation unit irradiating one of the first and second circuits with a control electromagnetic wave, and an unnecessary transition suppression electromagnetic wave irradiation unit irradiating one of the first and second circuits with an unnecessary interaction suppression electromagnetic wave.

Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.

Abstract: The present disclosure relates to a solid-state imaging device and electronic equipment that enable improvement of image quality of a captured image. In the solid-state imaging device, two or more photoelectric conversion layers including a photoelectric converter and a charge detector are laminated. The solid-state imaging device is configured to include a state in which light having entered one pixel of a first photoelectric conversion layer closer to an optical lens is received by the photoelectric converter of a plurality of pixels of the second photoelectric conversion layer farther from the optical lens. The technology of the present disclosure can be applied to, for example, a solid-state imaging device that performs imaging.

Abstract: The present disclosure provides a semiconductor device, a semiconductor structure and a formation method thereof, and relates to the field of semiconductor technologies. The formation method includes: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer to form trenches and through holes distributed side by side in the sacrificial layer; forming insulating layers covering a sidewall of the trench and a sidewall of the through hole; sequentially forming a conductive layer and a passivation layer in the trench and the through hole to form a bitline structure in the trench; and removing the passivation layer in the through hole to form a capacitor contact structure in the through hole.

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

Abstract: The disclosed light detecting element includes a first electrode, a second electrode, and a photoelectric conversion film arranged between the first electrode and the second electrode. The first electrode includes a first metal layer, a second metal layer arranged between the first metal layer and the photoelectric conversion film, and an oxide layer arranged between the second metal layer and the photoelectric conversion film and formed of an oxide of a metal that the second metal layer contains as a main component. The reflectance at the first electrode with respect to light having a certain wavelength transmitted through the photoelectric conversion film is higher than a reflectance specific to a material forming the second metal layer with respect to light having the certain wavelength.

Abstract: The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.