Abstract: The present disclosure provides a display substrate and a display apparatus. The display substrate includes a base substrate, including a display region and a frame region located on at least one side of the display region; a transistor, located on the base substrate, wherein the transistor is located in the display region and includes a gate, a first electrode and an active layer; and a protective structure, located on the base substrate, wherein the protective structure is provided in the frame region and close to the display region, and the protective structure is in the same layer as and is made of the same material as at least one of the active layer, the gate or the first electrode.

Abstract: The application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and multiple Word Lines (WLs), the multiple WLs extend along a first direction and are arranged on the substrate at intervals along a second direction, a WL isolation structure is arranged between every two adjacent WLs and includes at least a first isolation layer and a second isolation layer stacked along the second direction and made of different materials, and the first direction and the second direction intersect with each other.

Abstract: A semiconductor device may include: a first access line extending in a first direction; a second access line extending in a second direction intersecting the first direction; and a memory cell connected between the first access line and the second access line and including an electrode including a dielectric barrier therein.

Abstract: An imaging element includes plural pixels in each of which a photoelectric conversion unit and a charge holding unit that holds charges transferred from the photoelectric conversion unit are arranged in a first direction, the plural pixels include a first pixel, in the photoelectric conversion unit of the first pixel, a light-receiving region and a light shielding region are arranged in a second direction intersecting with the first direction, and a width of the photoelectric conversion unit in the second direction is larger than a width of the charge holding unit in the second direction.

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

Abstract: A ferroelectric memory device includes a substrate, a gate structure disposed over the substrate. The gate structure includes a plurality of gate electrode layers spaced apart from each other along a first direction substantially perpendicular to a surface of the substrate. The ferroelectric memory device includes a first electrode pillar and a second electrode pillar that extend along the first direction and are disposed to be spaced apart from each other in a second direction substantially parallel to the surface of the substrate inside a hole penetrating the gate structure, and a device isolation structure disposed to cross the first and second electrode pillars and to separate the gate structure over the substrate. The gate structure further includes a plurality of ferroelectric layers and a plurality of channel layers which are disposed to correspond to the plurality of gate electrode layers.

Abstract: A semiconductor device includes: a plurality of word line pad portions that are stacked over a lower structure in a direction perpendicular to a surface of the lower structure; horizontal-level dielectric layers between the word line pad portions; and bridge prevention layers disposed between the word line pad portions and covering ends of the horizontal-level dielectric layers.

Abstract: A photoelectric conversion device including pixels arranged in a semiconductor layer including first and second main surfaces is provided. Each of the pixels includes a first photodiode including a first region of a first conductivity type where signal charges are accumulated, a second photodiode arranged between the first region and the second main surface so as to at least partially overlap the first region, and including a second region of the first conductivity type where signal charges are accumulated, a third region of a second conductivity type arranged between the first and second region, and a first electrode arranged on the first main surface so as to cover the first region. Signal charges accumulated in the second region are transferred to the first region via a transfer portion formed in the third region by controlling a potential of the first electrode.

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same, and an object thereof is to provide a semiconductor and a method for manufacturing the same, the semiconductor device not diffusing a material of a metal layer to a semiconductor substrate. A semiconductor device of the present disclosure includes a semiconductor substrate which is formed of GaAs, a first barrier layer which is formed of an alloy containing Ni on the semiconductor substrate, a second barrier layer which is formed of Co or an alloy containing Co on the first barrier layer, and a metal layer which is formed on the second barrier layer. A Ni concentration in the first barrier layer is 80 at % or lower.

Abstract: Provided is an image sensor, which includes a first substrate that has a first surface and a second surface opposite to the first surface, and includes a pixel array area and an edge area, the edge area including a first conductive pad; an anti-reflection structure on the second surface; a pixel isolator in the first substrate and defining and separating pixels; and a micro lens array that is disposed on the anti-reflection structure, in which the anti-reflection structure includes a first insulating layer, a conductive layer, a second insulating layer, and a third insulating layer sequentially stacked, the conductive layer is on the pixel array area, and is not at least in a portion of the edge area where the first conductive pad is arranged, and a voltage is configured to be applied to the conductive layer.

Abstract: An imaging element according to the present disclosure includes a pixel, an overflow path, a pixel isolation unit, a pixel isolation electrode, an in-pixel isolation unit, and an in-pixel isolation electrode. The pixel includes a plurality of photoelectric conversion units formed in a semiconductor substrate having an interconnect region arranged on a front surface side and performs photoelectric conversion of incident light. The overflow path mutually transfers charges between the plurality of photoelectric conversion units. The pixel isolation unit is at a boundary of the pixel. The pixel isolation electrode is in the pixel isolation unit, and a first bias voltage is applied to the pixel isolation electrode. The in-pixel isolation unit isolates the plurality of photoelectric conversion units from each other. The in-pixel isolation electrode is arranged in the in-pixel isolation unit, and a second bias voltage is applied to the in-pixel isolation electrode.

Abstract: An electrically programmable fuse includes a first contact, a second contact spaced from the first contact, and a link between and electrically connecting the first contact and the second contact. The first contact, the second contact and the link include semiconductor material. A gate structure is partially over the link, leaving an uncovered link region uncovered by the gate structure. A silicide region is within the uncovered link region and provides an effective fuse link. The gate structure blocks silicide formation over an entirety of the fuse link, reducing the width of the effective fuse link, reducing the necessary programming current and the overall size of the electrically programmable fuse.

Abstract: The invention provides a display device and a display panel. The display device includes the display panel and a reading circuit. The display panel includes an upper substrate, a lower substrate, a thin-film transistor (TFT) layer, and a photosensitive circuit. The TFT layer is disposed between the upper substrate and the lower substrate. A plurality of TFTs of a pixel array of the display panel are disposed in the TFT layer. The photosensitive circuit is disposed in the TFT layer to sense an ambient light. The reading circuit is coupled to the photosensitive circuit to read a sensing result.

Abstract: A solid state image sensor according to an embodiment includes a transfer gate, a floating diffusion portion that converts signal charge transferred from a photodiode via the transfer gate into a voltage signal, and an extraction electrode that is formed of a film of conductive material including any of amorphous silicon, monocrystalline silicon, or N+ polysilicon, that has a peripheral edge portion surrounded by a film of insulating material and one end electrically connected to the floating diffusion portion, and that transmits the voltage signal.

Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.

Abstract: A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.

Abstract: The present application discloses a double-layer stacked CMOS image sensor, photo diode and transfer gate transistor of a pixel cell are formed on the first substrate sequentially along a longitudinal direction, and the other pixel transistors of the pixel cell are formed on the second substrate. The first substrate and the second substrate are packaged separately, and the second substrate is stacked on the top side of the first substrate instead of being in juxtaposition. Since the photo diode and the pixel transistors other than the transfer gate transistor of the pixel cell are located on two separate substrates respectively, the area of a photo diode region may be increased significantly, thereby greatly increasing full well capacitance of the image sensor and increasing a dynamic range, and reduce a dark current and image noise significantly, thereby improving the dark line noise and full well capacitance simultaneously.

Abstract: Embodiments of present invention provide a method. The method includes forming a set of metal pillars on a substrate; forming a negative-tone organic dielectric layer covering the set of metal pillars; planarizing the negative-tone organic dielectric layer to expose the set of metal pillars; forming a resist mask on the negative-tone organic dielectric layer, the resist mask having openings that expose the set of metal pillars; and forming a redistribution layer in the openings of the resist mask, the redistribution layer being in direct contact with the set of metal pillars. A structure formed thereby is also provided.

Abstract: A device wafer processing method includes a protective film forming step of forming a protective film that covers a face side of a device wafer, a mask forming step of, after the protective film forming step is carried out, applying a laser beam along streets and forming, in the protective film, a mask that has grooves extending along the streets, a device layer plasma etching step of, after the mask forming step is carried out, performing plasma etching on a device layer of the device wafer by device layer gas through the mask, and a base member plasma etching step of, after the device layer plasma etching step is carried out, performing plasma etching on the base member by base member gas through the mask.

Abstract: In a photoelectric conversion device, a first photoelectric conversion unit and a second photoelectric conversion unit are arranged so as to be aligned in a first direction in a plan view with respect to a substrate, the sensitivity of a third photoelectric conversion unit is lower than the sensitivity of the first photoelectric conversion unit and lower than the sensitivity of the second photoelectric conversion unit, and the third photoelectric conversion unit is arranged along a part of the outer circumference of a region including the first photoelectric conversion unit and the second photoelectric conversion unit in the plan view.