Patents Examined by Tucker J Wright
  • Patent number: 11127641
    Abstract: This spin current magnetization rotational element includes a first ferromagnetic metal layer for a magnetization direction to be changed, and a spin-orbit torque wiring extending in a second direction intersecting a first direction which is an orthogonal direction to a surface of the first ferromagnetic metal layer and configured to be joined to the first ferromagnetic metal layer, wherein the spin-orbit torque wiring has a structure in which a spin conduction layer joined to the first ferromagnetic metal layer and a spin generation layer joined to the spin conduction layer on a surface on a side opposite to the first ferromagnetic metal layer are laminated.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 21, 2021
    Assignee: TDK CORPORATION
    Inventors: Yohei Shiokawa, Tomoyuki Sasaki, Tomomi Kawano, Minoru Sanuki
  • Patent number: 11114493
    Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 7, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Johan Camiel Julia Janssens, Manuel H. Innocent, Sergey Velichko, Tomas Geurts
  • Patent number: 11107789
    Abstract: A method for manufacturing a semiconductor device according to the present invention includes at least the following three steps: (A) a step of preparing a first structure (100) including an adhesive laminate film (50) having a heat-resistant resin layer (10), a flexible resin layer (20) and an adhesive resin layer (30) in this order, and a first semiconductor component (60) adhered to the adhesive resin layer (30) and having a first terminal (65); (B) a step of performing solder reflow processing on the first structure (100) in a state where the first semiconductor component (60) is adhered to the adhesive resin layer (30); and (C) a step of, after the step (B), peeling the heat-resistant resin layer (10) from the adhesive laminate film (50).
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: August 31, 2021
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventor: Eiji Hayashishita
  • Patent number: 11088201
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsann Lin, Chien-Min Lee, Ji-Feng Ying
  • Patent number: 11088223
    Abstract: A display panel includes a substrate, a plurality of pixel units, a first color film, and an optical sensing layer. Each pixel subunit in each pixel unit includes a light-emitting portion. The optical sensing layer is sandwiched between the first color film and the substrate, configured to detect optical signals from an object facing the display panel, and includes a plurality of optical sensing portions, each arranged such that an orthographic projection thereof on the substrate is substantially covered by an orthographic projection of the first color film on the substrate, yet is not overlapped with an orthographic projection of the light-emitting portion of each pixel subunit on the substrate. A lens layer may be over the optical sensing layer, and an orthographic projection thereof on the substrate substantially covers an orthographic projection of each optical sensing portion on the substrate.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 10, 2021
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiang Feng, Sha Liu, Qiang Zhang, Zhaokun Yang, Xiao Sun, Ruizhi Yang, Yun Qiu
  • Patent number: 11088193
    Abstract: An image sensor includes a semiconductor substrate providing a plurality of pixel regions, a semiconductor photoelectric device disposed in each of the plurality of pixel regions, an organic photoelectric device disposed above the semiconductor photoelectric device, and a pixel circuit disposed below the semiconductor photoelectric device. The pixel circuit includes a plurality of driving transistors configured to generate a pixel voltage signal from an electric charge generated in the semiconductor photoelectric device and the organic photoelectric device. A driving gate electrode of at least one of the plurality of driving transistors has a region embedded in the semiconductor substrate.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gwi-Deok Ryan Lee, Myung Won Lee, Tae Yon Lee, In Gyu Baek
  • Patent number: 11088132
    Abstract: A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 10, 2021
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Guangyang Wang
  • Patent number: 11081632
    Abstract: The present disclosure relates to micro-LED chips, methods for manufacturing the same, and display devices. The micro-LED chip includes: a driving backplane including at least one first electrode, a groove being provided above the first electrode, and the first electrode being located at a bottom of the groove; the groove being filled with a conductive material, and the conductive material being obtained by curing a corresponding conductive ink; and a light emitting chip including at least one second electrode; and the first electrode is connected to the second electrode through the conductive material.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 3, 2021
    Assignee: CHENGDU VISTAR OPTOELECTRONICS CO., LTD.
    Inventors: Feng Zhai, Huimin Liu, Tao Wang
  • Patent number: 11075172
    Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: July 27, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Santo Alessandro Smerzi, Michele Calabretta, Alessandro Sitta, Crocifisso Marco Antonio Renna, Giuseppe D'Arrigo
  • Patent number: 11069718
    Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Koji Kusunoki
  • Patent number: 11049902
    Abstract: A light-emitting element wafer including a supporting substrate, a luminescent layer that is formed of a semiconductor and has a first surface and a second surface, the first surface including a first electrode, the second surface including a second electrode, the second surface being arranged between the supporting substrate and the first surface, a junction layer that joins luminescent layer to the supporting substrate and is arranged between the supporting substrate and the second surface, a first inorganic film formed on the first surface, a second inorganic film formed between the junction layer and the second surface, an isolation trench portion that isolates elements and is formed to have a depth such that the isolation trench portion extends from the first inorganic film to the supporting substrate, and a third inorganic film that connects the first inorganic film and the second inorganic film.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 29, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Daisuke Saito, Hiroki Naito, Takahiro Koyama, Sayaka Aoki, Arata Kobayashi
  • Patent number: 11043383
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 11031291
    Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Ming Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Hung-Chang Sun, Yao-Sheng Huang, Yu-Wei Lu, Fang-Wei Lee, Ziwei Fang, Huang-Lin Chao
  • Patent number: 11031322
    Abstract: There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 8, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yoshikatsu Miura
  • Patent number: 11018176
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 11011677
    Abstract: A display device is provided. The display device includes a substrate and a light-emitting unit disposed on the substrate. The light-emitting unit includes a transporting layer having a first semiconductor region and a second semiconductor region, and a conductive layer having a contact region that is in contact with the second semiconductor region. The distance between an edge of the contact region and an edge of the transporting layer is greater than or equal to 0.1 ?m.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 18, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Shun-Yuan Hu, Tsau-Hua Hsieh
  • Patent number: 11011453
    Abstract: A cooling apparatus for a semiconductor module including a semiconductor chip, having a case with a top plate, a base plate, a side wall plate arranged between the top plate and the base plate, and a coolant flow-through portion surrounded by the top plate, base plate, and side wall plate; first cooling pins secured to the top plate in the coolant flow-through portion of the case; and second cooling pins secured to the top plate in the coolant flow-through portion of the case and having lengths in a thickness direction from the top plate toward the base plate greater than lengths of the first cooling pins, wherein at least one first cooling pin and at least one second cooling pin are arranged in an alternating manner, and this pattern appears repeatedly at least twice, along a first direction in a plane parallel to the top plate.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 18, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Nobuhide Arai
  • Patent number: 11004927
    Abstract: A display apparatus including a substrate, a first power source line disposed in a peripheral area adjacent to a display area configured to display image, the first power source line including a first layer and a second layer disposed on the first layer and electrically connected to the first layer, a first insulation layer disposed between the first layer and the second layer of the first power source line, and a first insulating dam disposed on and contacting the second layer of the first power source line, the first insulating dam disposed in the peripheral area and surrounding the display area.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngjin Cho, Joong-Soo Moon, Cheol-Gon Lee, Yang Wan Kim, Changkyu Jin
  • Patent number: 10991908
    Abstract: A light-emitting unit (140) is formed on a substrate (100), and includes a light-transmitting first electrode (110), a light-reflective second electrode (130), and an organic layer (120) located between the first electrode (110) and the second electrode (130). A light-transmitting region is located between a plurality of light-emitting units (140). An insulating film (150) defines an end (142) of the light-emitting unit (140). A sealing member (200) is fixed to the light-emitting unit (140) directly or through an adhesive layer (210). In addition, a thickness of the substrate (100) is d, and a width of a portion of the second electrode (130) that is further on the outer side of the light-emitting unit (140) than the end (142) is W, d/2?W is established.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 27, 2021
    Assignee: PIONEER CORPORATION
    Inventor: Takeru Okada
  • Patent number: 10985092
    Abstract: A semiconductor device includes: a seal portion; a first electronic element; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from another end of the seal portion, the other end of the seal portion being along the longitudinal direction; a first connecting element disposed within the seal portion, and having one end that is electrically connected to the first electrode disposed on the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; and a conductive bonding agent.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 20, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama