Abstract: The present application discloses a double-layer stacked CMOS image sensor, photo diode and transfer gate transistor of a pixel cell are formed on the first substrate sequentially along a longitudinal direction, and the other pixel transistors of the pixel cell are formed on the second substrate. The first substrate and the second substrate are packaged separately, and the second substrate is stacked on the top side of the first substrate instead of being in juxtaposition. Since the photo diode and the pixel transistors other than the transfer gate transistor of the pixel cell are located on two separate substrates respectively, the area of a photo diode region may be increased significantly, thereby greatly increasing full well capacitance of the image sensor and increasing a dynamic range, and reduce a dark current and image noise significantly, thereby improving the dark line noise and full well capacitance simultaneously.

Abstract: A device wafer processing method includes a protective film forming step of forming a protective film that covers a face side of a device wafer, a mask forming step of, after the protective film forming step is carried out, applying a laser beam along streets and forming, in the protective film, a mask that has grooves extending along the streets, a device layer plasma etching step of, after the mask forming step is carried out, performing plasma etching on a device layer of the device wafer by device layer gas through the mask, and a base member plasma etching step of, after the device layer plasma etching step is carried out, performing plasma etching on the base member by base member gas through the mask.

Abstract: Embodiments of present invention provide a method. The method includes forming a set of metal pillars on a substrate; forming a negative-tone organic dielectric layer covering the set of metal pillars; planarizing the negative-tone organic dielectric layer to expose the set of metal pillars; forming a resist mask on the negative-tone organic dielectric layer, the resist mask having openings that expose the set of metal pillars; and forming a redistribution layer in the openings of the resist mask, the redistribution layer being in direct contact with the set of metal pillars. A structure formed thereby is also provided.

Abstract: In a photoelectric conversion device, a first photoelectric conversion unit and a second photoelectric conversion unit are arranged so as to be aligned in a first direction in a plan view with respect to a substrate, the sensitivity of a third photoelectric conversion unit is lower than the sensitivity of the first photoelectric conversion unit and lower than the sensitivity of the second photoelectric conversion unit, and the third photoelectric conversion unit is arranged along a part of the outer circumference of a region including the first photoelectric conversion unit and the second photoelectric conversion unit in the plan view.

Abstract: A semiconductor device includes semiconductor elements arranged in a first direction, an arm connection portion disposed between the semiconductor elements in the first direction, first and second power supply terminals disposed on the same side in the first direction, first and second substrates interposing the semiconductor elements therebetween, and a sealing body. The second substrate includes an insulating base member, a front-face metal body and a back-face metal body. The front-face metal body includes a second power supply wiring and a second relay wiring. The second power supply wiring includes a base portion on which the second element is arranged, and a pair of extending portions extending from the base portion in the first direction. The second relay wiring is disposed between the extending portions in a second direction, so that the second relay wiring and the base portion satisfy a relationship of L1<L2<L3.

Abstract: A method of manufacturing a high-frequency device includes mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer covering the first chip on the metal base, exposing an upper surface of the first pillar from the insulator layer, and forming a first wiring connected to the first pillar on the insulator layer and transmitting a high-frequency signal.

Abstract: Some embodiments relate to an integrated chip including a bottom electrode over a semiconductor substrate. A seed layer overlies the bottom electrode. A data storage structure is arranged on the seed layer. A first buffer layer is arranged between the bottom electrode and the seed layer. The first buffer layer is in physical contact with the seed layer and opposing sidewalls of the first buffer layer are aligned with opposing sidewalls of the seed layer.

Abstract: An apparatus is described having: a baseplate; an AC busbar mounted on the baseplate; a DC busbar having an upper DC busbar, a lower DC busbar and an insulating material therebetween, wherein the DC busbar is mounted such that the lower DC busbar is mounted to the baseplate and wherein the upper DC busbar has one or more openings through which the lower DC busbar is exposed; a first group of switching components mounted on the AC busbar, wherein the first group of switching components are connected to the upper DC busbar using first electrical connection means; and a second group of switching components mounted on the lower DC busbar, wherein at least one of the switching components of said second group of switching components is mounted within one of said openings, wherein the second group of switching components are to the AC busbar using second electrical connection means.

Abstract: An integrated sensor array device and method. The method includes providing a partially completed semiconductor substrate having a material stack used to form a sensor array device with a plurality of device regions. One or more isolation trench regions separating the device regions can be formed in a front-end isolation process during the formation of the device regions or in a back-end isolation process following a bonding process to integrate the sensor array device to an integrated circuit (IC) device. Prior to the front-end or back-end processing, metal interconnect materials within a passivation material can be formed via a planarization process to provide connection to n-type and p-type contact regions of the sensor array device. The resulting planarized sensor array device can then be bonded to the IC device, and a plurality of surface relief structures can be formed overlying a backside surface region of the planarized sensor array device.

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of insulating layers and a plurality of gate lines configured to be alternately stacked, and a cell plug configured to pass through the plurality of insulating layers and the plurality of gate lines, wherein the plurality of gate lines, each made of a conductive material, are etched together with the plurality of insulating layers, and the cell plug includes a blocking layer, a charge trap layer, a tunnel insulating layer, a channel layer, and a core pillar.

Abstract: Provided is a solid-state imaging element with which it is possible to minimize crosstalk between different pixel columns while suppressing a decrease in quantum efficiency of a photoelectric conversion unit due to a pixel separating section. The solid-state imaging element includes a plurality of pixels arranged in a two-dimensional matrix in the X direction and the Y direction and including a photoelectric conversion unit (N-type semiconductor thin film) containing a compound semiconductor. In addition, the solid-state imaging element includes a pixel separating section disposed only at a pixel boundary extending in the X direction.

Abstract: Various embodiments of the present application are directed toward an integrated chip (IC). The IC comprises a dielectric structure disposed over a substrate. A phase change material (PCM) structure is disposed over the dielectric structure. A first conductive structure and a second conductive structure are disposed over and electrically coupled to the PCM structure. A heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. The heating structure has a first surface and a second surface opposite the first surface. The first surface faces the PCM structure. The first surface has a first width and the second surface has a second width that is greater than the first width.

Abstract: An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.

Abstract: A semiconductor device includes: a first semiconductor structure including a stacked structure of a first dielectric layer and a first bonding dielectric layer; a second semiconductor structure including a stacked structure of a second dielectric layer and a second bonding dielectric layer; and a bonding pad penetrating the stacked structure of the first dielectric layer and the first bonding dielectric layer, and the stacked structure of the second dielectric layer and the second bonding dielectric layer, wherein the first bonding dielectric layer and the second bonding dielectric layer contact each other, and a first width of a first portion of the bonding pad penetrating the first dielectric layer is greater than each of a second width of a second portion of the bonding pad penetrating the first bonding dielectric layer, and a third width of a third portion of the bonding pad penetrating the second bonding dielectric layer.

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

Abstract: Photoelectric conversion apparatus including semiconductor layer includes pixel array region and peripheral region. The semiconductor layer has first and second faces. Each pixel includes first semiconductor region of first conductivity type arranged on the first face side and second semiconductor region of second conductivity type arranged on the second face side, and predetermined voltage causing avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region. The peripheral region includes third semiconductor region of the first conductivity type arranged on the first face side, fourth semiconductor region of the second conductivity type arranged apart from the third semiconductor region, and fifth semiconductor region of the first conductivity type arranged, close to the third semiconductor region, between the third semiconductor region and the fourth semiconductor region.

Abstract: Provided is an image sensor and a method of forming the same. The image sensor includes a first substrate having a first surface and a second surface opposite to each other; a plurality of photodetectors, disposed in the first substrate; and a plurality of color filters, disposed on the second surface of the first substrate and respectively corresponding to the plurality of photodetectors. The plurality of color filters are composed of a plurality of PIN diodes, and the plurality of PIN diodes are configured to absorb light of different wavelength ranges by applying different bias voltages.

Abstract: A laminated wiring has a first conductor which connects first terminals of one or more capacitors and each positive terminal of a plurality of semiconductor modules, a second conductor which connects second terminals of the one or more capacitors and each negative terminal of the plurality of semiconductor modules, and an insulator. Slits are cut in at least one of the first conductor and the second conductor (in both of them in the example of FIG. 1). By doing so, among the plurality of semiconductor modules, a variation in the total of respective inductance values between respective first terminals and one positive terminal closest to the respective first terminals and respective inductance values between respective negative terminals to one second terminal closest to the respective negative terminals becomes smaller than or equal to 10 nH.

Abstract: A display device includes a display area including a plurality of light emitting area including a first light emitting area, a second light emitting area, a third light emitting area, and a light blocking area disposed between adjacent ones of the plurality of light emitting areas, and a non-display area disposed adjacent to the display area, light emitting elements disposed on a substrate in each of the first light emitting area, the second light emitting area, and the third light emitting area, and a light conversion layer disposed on the light emitting elements. The light conversion layer includes a first wavelength conversion part disposed in the first light emitting area, a second wavelength conversion part disposed in the second light emitting area, a first light transmissive part disposed in the third light emitting area, and a bank disposed in the light blocking area. The non-display area is disposed on an edge of the display area.