Abstract: Various system embodiments for millimeter-wave chip packaging are disclosed in the present disclosure for smooth millimeter wave signal transition and good multi-channel signal isolation. The chip packaging features a substrate and a chip electrically connected using a plurality of metal pillars. A signal pillar and surrounding metal pillar may form a ground-signal-ground (GSG) pillar structure. A chip coplanar waveguide (CPW) structure may be formed on the chip around a signal path. A substrate CPW structure may also be form around a signal strip, which is electrically connected to the signal path. Characteristic impedances of the GSG pillar structure, the chip CPW structure and the substrate CPW structure may be within a predetermined range of each other to ensure smooth millimeter wave signal transition with minimum signal loss or distortion.

Abstract: The present disclosure relates to a solid-state imaging device and electronic equipment that enable improvement of image quality of a captured image. In the solid-state imaging device, two or more photoelectric conversion layers including a photoelectric converter and a charge detector are laminated. The solid-state imaging device is configured to include a state in which light having entered one pixel of a first photoelectric conversion layer closer to an optical lens is received by the photoelectric converter of a plurality of pixels of the second photoelectric conversion layer farther from the optical lens. The technology of the present disclosure can be applied to, for example, a solid-state imaging device that performs imaging.

Abstract: Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure.

Abstract: A light-emitting unit (140) is formed on a substrate (100), and includes a light-transmitting first electrode (110), a light-reflective second electrode (130), and an organic layer (120) located between the first electrode (110) and the second electrode (130). A light-transmitting region is located between a plurality of light-emitting units (140). An insulating film (150) defines an end (142) of the light-emitting unit (140). A sealing member (200) is fixed to the light-emitting unit (140) directly or through an adhesive layer (210). In addition, a thickness of the substrate (100) is d, and a width of a portion of the second electrode (130) that is further on the outer side of the light-emitting unit (140) than the end (142) is W, d/2 W is established.

Abstract: A terahertz element of an aspect of the present disclosure includes a semiconductor substrate, first and second conductive layers, and an active element. The first and second conductive layers are on the substrate and mutually insulated. The active element is on the substrate and electrically connected to the first and second conductive layers. The first conductive layer includes a first antenna part extending along a first direction, a first capacitor part offset from the active element in a second direction as viewed in a thickness direction of the substrate, and a first conductive part connected to the first capacitor part. The second direction is perpendicular to the thickness direction and first direction. The second conductive layer includes a second capacitor part, stacked over and insulated from the first capacitor part. The substrate includes a part exposed from the first and second capacitor parts.

Abstract: A wafer processing apparatus is configured to process a wafer by supplying mist to a surface of the wafer. The wafer processing apparatus includes a furnace in which the wafer is disposed, a gas supplying device configured to supply gas into the furnace, a mist supplying device configured to supply the mist into the furnace, and a controller. The controller is configured to execute a processing step by controlling the gas supplying device and the mist supplying device to supply the gas and the mist into the furnace, respectively. The controller is further configured to control the mist supplying device to stop supplying the mist into the furnace while controlling the gas supplying device to keep supplying the gas into the furnace when the processing step ends.

Abstract: An electronic device and a fabrication method thereof are provided. The electronic device includes a circuit structure layer, a package structure, an electronic element, and a plurality of function elements. The circuit structure layer has a first side and a second side opposite to the first side. The package structure is disposed on the first side of the circuit structure layer. The electronic element is embedded or encapsulated in the package structure. The function elements are disposed on the second side of the circuit structure layer. The function elements are electrically connected to the electronic element through the circuit structure layer. The electronic device provided by the disclosure exhibits borderless design or has a large function region.

Abstract: Embodiments of the invention are directed to an integrated circuit. A non-limiting example of the integrated circuit includes a transistor formed over a substrate. A dielectric region is formed over the transistor and the substrate. A trench is positioned in the dielectric region and over a S/D region of the transistor. A first liner and a conductive plug are within the trench such that the first liner and the conductive plug are only present within a bottom portion of the trench. A substantially oxygen-free replacement liner and a S/D contact are within the top portion of the trench such that a bottom contact surface of the S/D contact directly couples to a top surface of the conductive plug.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Abstract: According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.

Abstract: An LED light source module includes a substrate; a protective layer disposed on the substrate and having at least one opening; a plurality of conductive terminals disposed in the at least one opening, a light-emitting member, a plurality of electrodes, and an auxiliary structure. The conductive terminals include a first conductive terminal and a second conductive terminal. The light-emitting member includes a bottom surface, a light-emitting surface connected to the bottom surface, a back surface opposite to the light-emitting surface, at least one lateral surface connecting the light-emitting surface and the bottom surface.

Abstract: A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. The device further includes an electron system coupled to the resonator structure, and a gate positioned proximal to a portion of the electron system. The electron system and the gate are configured to interrupt the resonator structure at one or more predetermined locations forming a switch. The gate is configured to receive a gate voltage and vary an inductance of the electron system based upon the gate voltage. The varying of the inductance induces the resonator structure to vary a strength of coupling between the first device and the second device.

Abstract: Disclosed is a circuit assembly, in particular for a motor vehicle. The circuit assembly comprises a circuit board, an electronic component which is arranged on the circuit board and electrically connected to the circuit board via at least one electrical contact point, and a foamed material sealing element which seals off the electronic component and the at least one electrical contact point in media-tight fashion with respect to surroundings.

Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. A bonding insulating layer of the hybrid bonding structure extends to contact with one interconnect structure of the first die or the second die.

Abstract: A field effect transistor (FET) device includes a substrate, a gate structure over the substrate, a channel region under the gate structure, the channel region including a first semiconductor material, and a second semiconductor material interposed between the first semiconductor material and the substrate. The second semiconductor material is different from the first semiconductor material. An interface of the second semiconductor material with the first semiconductor material has facets. A surface of the second semiconductor material interfacing with the substrate is non-planar.

Abstract: The present disclosure provides a method for preparing a semiconductor device with a composite dielectric structure. The method includes forming a photoresist pattern structure over a first semiconductor die. The method also includes forming a second dielectric layer surrounding the photoresist pattern structure, and removing the photoresist pattern structure to form a first opening in the second dielectric layer. The method further includes forming dielectric spacers along sidewalls of the first opening, and forming an interconnect structure surrounded by the dielectric spacers. In addition, the method includes bonding a second semiconductor die to the second dielectric layer. The second semiconductor die includes a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.

Abstract: A semiconductor device includes metal connector plate having a first lower surface, facing an electrode of a semiconductor chip, a first end surface, a second end surface, and a second lower surface connecting the first end surface and the second end surface. In a first direction parallel to the semiconductor chip, an end surface of the electrode is located between the positions of the first end surface and the second end surface. A distance from the second lower surface to the electrode is greater than a distance from the first lower surface to the electrode. A joining component has a first portion between the first lower surface and the electrode and a second portion between the second lower surface and the electrode.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming an organosilicon compound layer on a surface of an oxide semiconductor substrate, heating the oxide semiconductor substrate provided with the organosilicon compound layer at a first temperature to form a silicon diffusion layer inside the oxide semiconductor substrate, and removing the organosilicon compound layer from the surface of the oxide semiconductor substrate after heating the oxide semiconductor substrate at the first temperature.

Abstract: An electronic component embedded substrate includes a core structure including a first insulating body and core wiring layers and having a cavity and having a stopper layer disposed as a bottom surface; an electronic component disposed in the cavity and attached to the stopper layer; and a build-up structure including a second insulating body covering at least a portion each of the core structure and the electronic component and filling at least a portion of the cavity, and build-up wiring layers wherein the stopper layer has a first region in which a portion of one surface is exposed from the first insulating body and a second region in which the other portion of one surface is covered with the first insulating body, and a surface roughness of one surface of the stopper layer in the first region is greater than that of the stopper layer in the second region.