Abstract: A photo receiver includes a photo detector including a semiconductor substrate having a first main surface and a second main surface and a metal pattern layer provided on the second main surface; and a carrier including a supporting substrate having a third main surface facing the second main surface and a solder pattern layer provided on the third main surface. The solder pattern layer is bonded to the metal pattern layer. The first main surface is provided with a variable optical attenuator, an optical 90-degree hybrid device, and a plurality of photodiodes optically coupled to the variable optical attenuator via the optical 90-degree hybrid device. The solder pattern layer and the metal pattern layer are located in a peripheral area surrounding a central area where the variable optical attenuator and the optical 90-degree hybrid device are located when viewed in the normal direction of the first main surface.

Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.

Abstract: Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.

Abstract: A foldable display device having a foldable display region includes a flexible substrate, a plurality of first light emitting units disposed on the flexible substrate in the foldable display region, and a first protector disposed on at least one of the first light emitting units. The first protector has a surface, and at least a portion of the surface has a curved profile.

Abstract: Temperature sensor packages and methods of fabrication are described. The temperature sensor packages in accordance with embodiments may be rigid or flexible. In some embodiments the temperature sensor packages are configured for touch sensing, and include an electrically conductive sensor pattern such as a thermocouple or resistance temperature detector (RTD) pattern. In some embodiments, the temperature sensor packages are configured for non-contact sensing an include an embedded transducer.

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

Abstract: Methods for depositing a silicon germanium tin boron (SiGeSn:B) film on a substrate are described. The method comprises exposing a substrate to a precursor mixture comprising a boron precursor, a silicon precursor, a germanium precursor, and a tin precursor to form a boron silicon germanium tin (SiGeSn:B) film on the substrate.

Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

Abstract: An image sensor includes a semiconductor layer including a first section and a second section, the semiconductor layer having a first surface and a second surface that face each other; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a first grid pattern on the first surface of the semiconductor layer over the first section; and a light-shield pattern on the first surface of the semiconductor layer over the second section. A top surface of the first grid pattern is located at a first level, a top surface of the light-shield pattern is located at a second level, the first level is lower than the second level, and the first and second levels are defined with respect to the first surface of the semiconductor layer.

Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.

Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.

Abstract: A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire.

Abstract: A chip-scale package type light emitting diode is provided. In the light emitting diode according to one embodiment, an opening exposing a pad metal layer is separated from an opening of a lower insulation layer which exposes an ohmic reflection layer formed on a mesa. Therefore, it is possible to prevent solder, particularly Sn, from diffusing and contaminating the ohmic reflection layer.

Abstract: A display device includes a light-emitting element layer on the substrate and having a display area for displaying images, and a sealing layer covering the light-emitting element layer. The sealing layer includes a first inorganic film, an organic film on the first inorganic film, a second inorganic film on the organic film, and a third inorganic film. The first inorganic film and the second inorganic film are in contact with each other around the organic film. The third inorganic film, without overlapping with the display area, covers a peripheral portion of the organic film.

Abstract: A display apparatus including a substrate, a first power source line disposed in a peripheral area adjacent to a display area, the first power source line including a first layer and a second layer electrically connected to each other, a first gate pattern disposed between the first layer of the substrate and including a first gate fan-out line in the peripheral area and a first gate connecting line connected to the first gate fan-out line and extending between the first gate fan-out line and the display area, a first insulation layer disposed between the first layer and the second layer of the first power source line, a second insulation layer disposed between the first insulation layer and the second layer, and a first insulating dam disposed on and contacting the second layer, the first insulating dam disposed in the peripheral area and surrounding the display area.

Abstract: There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element.