Abstract: A terahertz element of an aspect of the present disclosure includes a semiconductor substrate, first and second conductive layers, and an active element. The first and second conductive layers are on the substrate and mutually insulated. The active element is on the substrate and electrically connected to the first and second conductive layers. The first conductive layer includes a first antenna part extending along a first direction, a first capacitor part offset from the active element in a second direction as viewed in a thickness direction of the substrate, and a first conductive part connected to the first capacitor part. The second direction is perpendicular to the thickness direction and first direction. The second conductive layer includes a second capacitor part, stacked over and insulated from the first capacitor part. The substrate includes a part exposed from the first and second capacitor parts.

Abstract: A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.

Abstract: A semiconductor device package includes a semiconductor die and an anisotropic thermal conductive structure. The semiconductor die includes a first surface, a second surface opposite to the first surface and edges connecting the first surface to the second surface. The anisotropic thermal conductive structure has different thermal conductivities in different directions. The anisotropic thermal conductive structure includes at least two pairs of film stacks, and each pair of the film stacks comprises a metal film and a nano-structural film alternately stacked. The anisotropic thermal conductive structure comprises a first thermal conductive section disposed on the first surface of the semiconductor die, and the first thermal conductive section is wider than the semiconductor die.

Abstract: An electronic component has a base 10; an electronic element 20 provided on one side of the base 10; a connecting body 30 provided on one side of the electronic element 20; a heat dissipating block 40 provided on one side of the connecting body 30; an insulating part 50 provided between the connecting body 30 and the heat dissipating block 40; and a sealing part 90 in which the electronic element 20, the connecting body 30 and the insulating part 50 are sealed. At least a part of a surface on another side of the base 10 is exposed from the sealing part 90. At least a part of a surface on one side of the heat dissipating block 40 is exposed from the sealing part 90.

Abstract: There is a problem that the reliability of insulation is lowered. A length L2 from a center P of a conductor layer 334 to a peripheral edge portion of an insulating member 333 is formed to be longer than a length L1 from the center P of the conductor layer 334 to a peripheral edge portion of a protruding portion 307a of a base member 307. In other words, a base end surface 308 of the peripheral edge portion of the protruding portion 307a is located on an inner side with respect to an insulating member end surface 336 of the peripheral edge portion of the insulating member 333. Further, the insulating member end surface 336 of the insulating member 333 and a conductor layer end surface 344 of the conductor layer form an end surface at the same position.

Abstract: A thin film transistor and its manufacturing method, a display panel, and a display device are provided. The thin film transistor includes an insulating layer on an active layer; the insulating layer includes m sub-insulating layers which are alternately stacked, and any two adjacent sub-insulating layers in the m sub-insulating layers have different refractive indexes, and m is an integer not less than 2.

Abstract: A semiconductor device with an array of vertically stacked electrochemical random-access memory (ECRAM) devices, includes holes formed in a vertical stack of horizontal electrodes. The horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers. The semiconductor device includes a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and holes. Selector layers fill holes. The selector layers include an inner selector layer and outer selector layers. The channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer and a fill layer is deposited over the vertical stack. The fill layer has been reduced down to the top of the inner selector layer.

Abstract: In some examples, an integrated circuit includes a plurality of power modules formed on a substrate, including a first power module located between second and third power modules. The first power module is configured to conduct a load current, and includes a power transistor and first and second sense transistors. The first sense transistor is disposed at a first position between the second power module and a central axis of the first power module, and the second sense transistor is disposed at a second position between the third power module and the central axis. The first sense transistor is configured to conduct a first sense current; and the second sense transistor is configured to conduct a second sense current. The first and second sense transistors are configured to direct the first and second sense currents toward a measurement circuit that is configured to determine a derived sense current indicative of the load current.

Abstract: A display device includes a light-emitting element layer on the substrate and having a display area for displaying images, and a sealing layer covering the light-emitting element layer. The sealing layer includes a first inorganic film, an organic film on the first inorganic film, a second inorganic film on the organic film, and a third inorganic film. The first inorganic film and the second inorganic film are in contact with each other around the organic film. The third inorganic film, without overlapping with the display area, covers a peripheral portion of the organic film.

Abstract: A lighting structure according to embodiments of the invention includes a semiconductor light emitting device and a flat wavelength converting element attached to the semiconductor light emitting device. The flat wavelength converting element includes a wavelength converting layer for absorbing light emitted by the semiconductor light emitting device and emitting light of a different wavelength. The flat wavelength converting element further includes a transparent layer. The wavelength converting layer is formed on the transparent layer.

Abstract: Embodiments of the present invention are directed to a new crack stop system and a method for providing an interlayer dielectric (ILD) crack bifurcation in semiconductor back-end-of-line (BEOL). In a non-limiting embodiment of the invention, a crack stop is formed over a substrate. The crack stop can span one or more dielectric layers. A topologically interlocking composite structure is formed adjacent to the crack stop and over the substrate. The topologically interlocking composite structure spans the one or more dielectric layers. A capping film is formed over the topologically interlocking composite structure and one or more metal interconnect layers are formed over the capping film. The composite structure includes a bulk matrix material and embedded inclusions. To promote crack bifurcation, materials of the inclusions and bulk matrix material are selected to ensure that the Young's modulus of the inclusions is greater than the Young's modulus of the bulk matrix material.

Abstract: This spin current magnetization rotational element includes a first ferromagnetic metal layer for a magnetization direction to be changed, and a spin-orbit torque wiring extending in a second direction intersecting a first direction which is an orthogonal direction to a surface of the first ferromagnetic metal layer and configured to be joined to the first ferromagnetic metal layer, wherein the spin-orbit torque wiring has a structure in which a spin conduction layer joined to the first ferromagnetic metal layer and a spin generation layer joined to the spin conduction layer on a surface on a side opposite to the first ferromagnetic metal layer are laminated.

Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes at least the following three steps: (A) a step of preparing a first structure (100) including an adhesive laminate film (50) having a heat-resistant resin layer (10), a flexible resin layer (20) and an adhesive resin layer (30) in this order, and a first semiconductor component (60) adhered to the adhesive resin layer (30) and having a first terminal (65); (B) a step of performing solder reflow processing on the first structure (100) in a state where the first semiconductor component (60) is adhered to the adhesive resin layer (30); and (C) a step of, after the step (B), peeling the heat-resistant resin layer (10) from the adhesive laminate film (50).

Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

Abstract: A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.

Abstract: A display panel includes a substrate, a plurality of pixel units, a first color film, and an optical sensing layer. Each pixel subunit in each pixel unit includes a light-emitting portion. The optical sensing layer is sandwiched between the first color film and the substrate, configured to detect optical signals from an object facing the display panel, and includes a plurality of optical sensing portions, each arranged such that an orthographic projection thereof on the substrate is substantially covered by an orthographic projection of the first color film on the substrate, yet is not overlapped with an orthographic projection of the light-emitting portion of each pixel subunit on the substrate. A lens layer may be over the optical sensing layer, and an orthographic projection thereof on the substrate substantially covers an orthographic projection of each optical sensing portion on the substrate.

Abstract: An image sensor includes a semiconductor substrate providing a plurality of pixel regions, a semiconductor photoelectric device disposed in each of the plurality of pixel regions, an organic photoelectric device disposed above the semiconductor photoelectric device, and a pixel circuit disposed below the semiconductor photoelectric device. The pixel circuit includes a plurality of driving transistors configured to generate a pixel voltage signal from an electric charge generated in the semiconductor photoelectric device and the organic photoelectric device. A driving gate electrode of at least one of the plurality of driving transistors has a region embedded in the semiconductor substrate.