Abstract: An electronic device including a plurality of micro-lenses, a light-limiting structure, a first light-transmitting structure, and a sensing element is provided. The plurality of micro-lenses are arranged in an array. The sensing element includes a plurality of sensing pixels. The sensing element, the first light-transmitting structure, the light-limiting structure, and the plurality of micro-lenses are sequentially stacked in a stacking direction. Each of the plurality of sensing pixels corresponds to at least two of the plurality of micro-lenses in the stacking direction.

Abstract: A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.

Abstract: RF amplifiers are provided that include a submount such as a thermally conductive flange. A dielectric substrate is mounted on an upper surface of the submount, the dielectric substrate having a first outer sidewall, a second outer sidewall that is opposite and substantially parallel to the first outer sidewall, and an interior opening. An RF amplifier die is mounted on the submount within the interior opening of the dielectric substrate, where a longitudinal axis of the RF amplifier die defines a first axis. The RF amplifier die is positioned so that a first angle defined by the intersection of the first axis with the first outer sidewall is between 5° and 45°. The dielectric substrate may be a ceramic substrate or a dielectric layer of a printed circuit board.

Abstract: Provided is a semiconductor package. More particularly, the present invention relates to a clip, a lead frame, and a substrate used in a semiconductor package having engraved patterns formed on surfaces thereof so as to increase an adhesive force and a corrosion resistant performance, thereby improving reliability of the semiconductor package, and the semiconductor package including the same.

Abstract: An object of the invention is to improve the reliability of a power semiconductor device. The power semiconductor device according to the invention includes a semiconductor element, a first terminal and a second terminal that transmit current to the semiconductor element, a first base and a second base that are disposed to face each other while interposing a part of the first terminal, a part of the second terminal, and the semiconductor element between the first base and the second base, and a sealing material that is provided in a space between the first base and the second base. The second terminal includes an intermediate portion formed in such a way that a distance from the first terminal increases along a direction away from the semiconductor element. The intermediate portion is provided between the first base and the second base and in the sealing material.

Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

Abstract: An image sensor includes a semiconductor layer including a first section and a second section, the semiconductor layer having a first surface and a second surface that face each other; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a first grid pattern on the first surface of the semiconductor layer over the first section; and a light-shield pattern on the first surface of the semiconductor layer over the second section. A top surface of the first grid pattern is located at a first level, a top surface of the light-shield pattern is located at a second level, the first level is lower than the second level, and the first and second levels are defined with respect to the first surface of the semiconductor layer.

Abstract: A structure includes: a plurality of through holes that are provided to an insulating base and penetrate the insulating base in the thickness direction; conductive paths that are constituted of a conductive substance filling the plurality of through-holes; and insulators with which the plurality of through-holes are filled and are constituted of an insulating substance different from that of the insulating base. Both ends of the respective conductive paths are provided with protrusions that protrude from each surface of the insulating base in the thickness direction. Both ends of the insulators are flush with each surface of the insulating base in the thickness direction, protrude with respect to the surface in the thickness direction, or are recessed from the surface in the thickness direction.

Abstract: To provide a back-illuminated solid-state imaging device that can improve image quality. Provided is a back-illuminated solid-state imaging device that includes at least a semiconductor substrate, an organic photoelectric conversion film, and an optical waveguide. The organic photoelectric conversion film is formed on one of front and back surfaces of the semiconductor substrate. The optical waveguide is formed between the semiconductor substrate and the organic photoelectric conversion film.

Abstract: A transistor (2) and a matching circuit substrate (3-6) are provided on a base plate (1) and connected to each other. A frame (15) is provided on the base plate (1) and surrounds the transistor (2) and the matching circuit substrate (3-6). The frame (15) has a smaller linear expansion coefficient than that of the base plate (1). A screwing portion (17) is provided in the frame (15). A size of the base plate (1) is smaller than that of the frame (15).

Abstract: The present disclosure provides an array substrate, a method of manufacturing the same, and a display panel. The array substrate includes a base substrate, a thin film transistor disposed at a side of the base substrate. The thin film transistor includes a first electrode, a second electrode, and a gate electrode. The array substrate includes a data line disposed at the side of the base substrate The array substrate includes a connection electrode electrically connecting the first electrode of the thin film transistor to the data line. An orthographic projection of an active layer of the thin film transistor on the base substrate is located within an orthographic projection of the gate electrode of the thin film transistor on the base substrate.

Abstract: Temperature sensor packages and methods of fabrication are described. The temperature sensor packages in accordance with embodiments may be rigid or flexible. In some embodiments the temperature sensor packages are configured for touch sensing, and include an electrically conductive sensor pattern such as a thermocouple or resistance temperature detector (RTD) pattern. In some embodiments, the temperature sensor packages are configured for non-contact sensing an include an embedded transducer.

Abstract: An electronic module has a sealing part 90; a rear surface-exposed conductor 10, 20, 30 having a rear surface-exposed part 12, 22, 32 whose rear surface is exposed; a rear surface-unexposed conductor 40, 50 whose rear surface is not exposed; an electronic element 15, 25, which is provided in the sealing part 90 and provided on a front surface of the rear surface-exposed conductor 40, 50; a first connector 60 for electrically connecting the electronic element 15, 25 with the rear surface-exposed conductor 10, 20, 30; and a second connector 70 for electrically connecting the electronic element 15, 25 with the rear surface-unexposed conductor 40, 50. A thickness T1 of the first connector 60 is thicker than a thickness T2 of the second connector 70.

Abstract: Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure.

Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.

Abstract: In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.

Abstract: A semiconductor device includes an interconnect structure disposed over a first semiconductor die. The first semiconductor die includes a semiconductor substrate and a first conductive pad disposed over the semiconductor substrate, and the first conductive pad is covered by the interconnect structure. The semiconductor device also includes dielectric spacers surrounding the interconnect structure. An interface between the dielectric spacers and the interconnect structure is curved. The semiconductor device further includes a dielectric layer surrounding the dielectric spacers, and a second semiconductor die bonded to the dielectric layer and the interconnect structure. The second semiconductor die includes a second conductive pad, and the interconnect structure is covered by the second conductive pad.

Abstract: A thermal management package for a semiconductor device includes a high dielectric constant material substrate, a high thermal conductivity slug disposed in a first window in the high dielectric constant material substrate and held therein by a first bonding material, an outer substrate formed from a material having a low dielectric constant and having a second window formed therein, the high dielectric constant material substrate disposed in the second window in the low dielectric constant outer substrate and held therein by a second bonding material.

Abstract: A biological information detecting apparatus includes: an LC resonant pressure sensor including a resonant circuit including a capacitor and an inductor, and having a resonant frequency that changes depending on a change in external pressure applied to the capacitor; and an integrated circuit (IC) chip package including a coil type antenna radiating a radio frequency (RF) signal within a preset frequency band, wherein a change in the resonant frequency results in a change in a power transmission rate depending on a inductive coupling between the resonant frequency and a frequency of the RF signal. The IC chip package includes the coil type antenna disposed in a region overlapping the LC resonant pressure sensor in a plan view of the IC chip package.

Abstract: A monolithic multi-metallic thermal expansion stabilizer (MTES) has a coefficient of thermal expansion (CTE) differential between a first surface and a second surface, and a transition region extending between for mitigating the CTE differential.