Abstract: A scalable visualization system includes a plurality of scalable tiles (10) that each comprise a display portion (18) and a processing portion (20). Each of the display portions (18) define a portion of a physical display space. Each of the processing sections defines a processing node in the parallel processing system. The parallel processing system operating on a single node or a plurality of nodes. A message fabric (36) is provided to connect CPU nodes (34) and each of the tiles (10) together. The tiles (10) are scaled by interconnecting them to form the desired display space with each of the display elements (18). As each tile (10) is added to the overall display space, an additional CPU node (34) is also added, such that not only is the display space scaled up from a physical coordinant standpoint, but the processing power is also scaled up. In addition, each of the CPU nodes (34) is operable to update an associated display list (28) that defines the parameters of the display element (18 ).

Abstract: A method and system for a graphical hardware description and testing interface is provided for use in conjunction with a data processing system. A polling system is provided for determining the configuration of the data processing system, including identification of the components. A graphic display is coupled to the polling system and utilized to display a graphic depiction of the data processing system, including any components. This graphic depiction is displayed in response to a determination of the configuration of the data processing system. The graphical hardware description and testing interface also includes a testing program for selectively testing a particular component to determine whether the component is defective. Also included is a display control circuit coupled to the graphic display. This display control circuit is utilized to selectively alter the graphic depiction of the data processing system, including any components, in response to the testing of the component.

Abstract: A CPU or other graphics processor provides a pixel data stream to a graphics controller over a system bus. The pixel data stream includes a graphics controller address as well as a pixel type tag, which in the presently preferred embodiment comprises 4 bits. In addition to the graphic controller address and pixel type tag, a pixel address and pixel data are provided. The pixel type tag identifies the "type" of pixel data in the data stream supplied to the graphics controller. If the data identified by the pixel type tag corresponds to the type of data which the frame buffer is configured for, then the data provided over the system bus is simply passed through the graphics controller and written at the appropriate pixel address in the frame buffer.