Abstract: A digital video editor employing a single chip special-purpose digital video processing unit (VPU) having the capability to combine several different digital video input signals into a single digital video output signal is disclosed. The VPU comprises a microprocessor operating under a set of instructions which is operative for receiving, storing and manipulating portions of an incoming digital video signal and a delay circuit, coupled to the microprocessor, for delaying execution of a particular instruction if a particular portion upon which the instruction is to operate has not yet been stored. The VPU processes multiple digitized video signals in real time in a time-sharing fashion because its processing speed is substantially greater than the rate at which it receives video data and processes multiple picture elements of a single digital stream simultaneously. In a preferred environment, The VPU operates in conjunction with an IBM compatible personal computer, an inexpensive general purpose computer.

Abstract: A draw processor for a graphics accelerator is disclosed that performs edgewalking and scan interpolation functions to render a three dimensional geometry object defined by a draw packet. The draw processor renders a subset of pixels on a scan line, such that a set draw processors taken together render the entire geometry object. The draw processor renders pixels into an interleave bank of a multiple bank interleaved frame buffer. The draw processor also processes direct port data through a direct port pipeline.

Abstract: A method and apparatus for updating data stored in a write once/read many memory which comprises creating a virtual image of data stored in the memory, updating data in the virtual image of the memory and designating updated data in the virtual image, and writing designated updated data from the virtual image to the memory. In the virtual image there is a main journal for organizing file information on the memory and file journals for each file stored on the memory. Each file journal contains self-describing information for its corresponding file.

Abstract: Hardware logic and processing methods for enhanced data manipulation within a graphics display system are described. The graphics display system includes a graphics processor sub-system and a rendering subsystem which are serially connected for pipeline processing of an interleaved stream of commands and data. One or more status bits or XBITs are defined within each rasterizer of a multi-rasterizer rendering sub-system. An XBIT, which may comprise a ZBIT, a UBIT, or an RBIT, etc., provides a mechanism for introducing execution of various logic functions within the rendering sub-system portion of the computer graphics adapter. Corresponding data processing methods are also described.

Abstract: A method and apparatus for the management of the data associated with multiple graphics contexts in a computer graphics rendering system. Graphics contexts are built by graphics engines and selectively saved into a context save RAM. Context switches are managed either by modifying a context base pointer to address a new section of the context save RAM, or by writing out a portion of the context save RAM to external storage and reading in a replacement context from external storage. The writing and reading process are managed by a control processor allowing the graphics engines to switch context at the same time. New contexts read from external storage automatically cause regeneration of downstream rasterization parameters.

Abstract: A computer system is connected to a printer via a parallel interface, for point-of-sale (POS) applications employing one or more different paper sources, such as, continuous tape, document insertion, and sheet validation. A detector is associated with each paper source to sense a paper empty or out condition. The printer has an addressable latch that enables a choice of one or more of these detectors for connection through to a single status line within the parallel printer interface. The computer CPU can access the addressable latch prior to any printing so that the presence of an appropriate type of paper in its appropriate print position in the printer can be checked or tested utilizing an industry standard parallel printer interface, such as, the widely employed Centronics interface.

Abstract: A method and means which upon detecting indicia embedded in a decoded run length coded bit string skips over a range of bit memory mapped addresses thus reducing the number of write operations into a counterpart bit mapped memory. The coded indicia include portions which specify a skip and a skip range for storage locations in said bit mapped memory.

Abstract: A random access memory system organized such that multiple pixels may be accessed when one row column address is provided. The random access memory system includes a first group of random access memory devices and a second group of random access memory devices. The first group of devices stores information for pixels on an even horizontal scan line and the second group of devices stores information for pixels on an odd horizontal scan line. An address generator of the random access memory system generates an address to access information from the first group of devices for one pixel and information from the second group of devices for another pixel.

Abstract: A video signal is received from an asynchronous link (15) at an irregular frame rate for display on a computer monitor 9 at a regular frame rate. Frames are transferred to the monitor via first and second buffers (23, 25). A control process (27) manages the transfer of frames between the first and second buffers and is responsible for deciding if, when and how many frames to transfer, in order to minimise the delay between the incoming image and the displayed image.

Abstract: There is provided a printing system for producing prints from a print job written in one of a plurality of page description languages with the print job assuming the form of a print job stream. The printing system includes a plurality of page description language analyzing units for sampling the print job stream, each analyzing unit outputting an information signal which provides information regarding the print job stream. A filter, which receives the information signals, processes the information signals and outputs a filtered signal which indicates the page description language in which the print job is written.

Abstract: A printer control device is employed with host computer controlled printers, typically of the point-of-sale (POS) type, which are capable of printing on several different types of recording paper. Several detectors are used on the printer to sense out-of-paper conditions with at least one detector being associated with each paper source used, and a detector selection device is used to determine which detector outputs are to be connected to the host computer through a communications interface. Detector output values can be stored and logically combined to allow transfer over a single communications line. Specific detector outputs can be enabled or selected for transfer to the host or for use in termination of printing operations. A paper type selector is used for setting line spacing or advancement amounts which are stored by the printer controller for later retrieval. Typically each advancement value relative to one type of paper is stored separately in a memory location or element.

Abstract: A processing system operating on data words having first and second portions includes a memory bank comprising first and second memories each with associated first and second set of address inputs. First memory includes a first storage location storing the first portion of a first word accessible by a set of address bits received at the first inputs and a second set of address bits received at the second inputs. The first memory further includes a second storage location storing the second portion of a second word accessible by the first set of bits received at the first inputs and a third set of bits received at the second inputs. Second memory includes a first storage location storing the second portion of the second word accessible by the first set of bits received at the first inputs and the second set of bits received at the second inputs.

Abstract: Video display apparatus having multiple processors for operation in parallel, each processing a respective complete video image in the sequence of video images (fields or frames) which form a video picture, the processing being in accordance with a selected signal processing algorithm. The algorithm may be one which simulates a signal processing circuit design which is to be evaluated, so that the effect of changes in circuit design can be displayed in real time. The signal data for each of the sequential video images is assembled into data packets in successive equal time slots, which are transmitted downstream on a data bus along which are a succession of data processors. The headers of the packets for a given image identify a serially corresponding processor to which such image is assigned, and such packets are processed by the assigned processor in accordance with the selected algorithm.

Abstract: An image editing system for transmission network supervision for comprehensibly displaying the status of a plurality of stations and the transmission routes connecting them in a specific area. Initially, station data are created as a data source for graphically displaying each of the stations within the area. The station data are stored in a first memory. Then area data are created as a data source for graphically displaying a map of the area. The area data are stored in a second memory. Map data are also created to display graphically an area map based on the station data and area data. The map data are stored in a third memory. The area map includes an image map that is a map of the area reduced to a desired scale, the multiple stations superimposed on the image data, and the transmission routes connecting these stations. The area map is displayed on a monitor by use of the map data retrieved from the third memory.

Abstract: A method of transmitting frames of video data to be displayed including the steps of receiving at least a portion of a frame of video data, determining whether the received video data can be stored in a buffer, storing the received video data in a buffer if the received video data can be stored in the buffer, and erasing any video data of the frame of video data if the received video data cannot be stored in the buffer. In addition, an apparatus for transmitting frames of video data to be displayed including an apparatus for receiving at least a portion of a frame of video data, an apparatus for determining whether the received video data can be stored in a buffer, an apparatus for storing the received video data in the buffer if the received video data can be stored in the buffer, and an apparatus for erasing any video data of the frame of video data if the received video data cannot be stored in the buffer.

Abstract: A display memory system consisting of a controller and a display memory that has a read display memory cycle time that is a non-integer multiple of the write display memory update rate. The display memory being partitioned into two frames of display memory with each frame having a plurality of subframes. The controller consisting of a read display memory decoder, a read display memory next subframe generator a read display memory latch and consisting of a write display memory decoder, a write display memory next subframe generator and write display memory latch.

Abstract: A plurality of linework data including run length data are combined at a high speed and without reconverting run-length data to pixel image data. During the combining operation based on linework data stored in a linework operation memory 50, subsequent linework data is supplemented from an external storage unit 64 to an input linework memory 48. When one of the plurality of linework data in the linework operation memory is used up, the supplement of linework data is transferred from the input linework memory to the linework operation memory, both of which are random access memories. In the combining process of run-length data, unit-run data are respectively extracted from each linework data according to the value of a current position pointer representing an end point of the run which has already been combined. Combined unit-run data is produced by comparing the working data for the plurality of linework data.

Abstract: A graphics movement control system on a display screen controls the intervals between drawing graphics according to the number of picture elements of the graphics when the graphics are moved on a display screen using a pointing device such as a mouse, etc. in an editor for editing a block diagram and a circuit diagram through a workstation, etc. When graphics displayed on a display screen are moved by a pointing device, the drawing intervals between in moving the graphics are controlled. Thus, the number of times to draw the graphics can be controlled between the starting point and the ending point of the movement on the display screen. That is, the complexity of the graphics is determined by the number of picture elements forming the graphics. The intervals between drawing graphics on the display screen are lengthened for those having a large number of picture elements so that the number of times to draw the graphics up to the final movement position is reduced.

Abstract: A method of controlling an image memory system wherein non-interlace image data is written into the odd field and the even field memories, and the contents written into the odd field and even field memories are respectively read out so as to be converted into interlace image data. Each line of the non-interlace image data is alternately written into the odd field and even field memories in units of a plurality of dots. If the plurality of dots include dots for the odd field and dots for the even field, the image data of the plurality of dots are simultaneously written into both the odd field memory and the even field memory. When reading the image data out from the odd field memory, the image data for the even field written into the odd field memory is invalidated. Similarly, when reading the image data out from the even field memory, the image data for the odd field written into the even field memory is invalidated.

Abstract: A document processing system controls the printing of documents represented in page description language form. Documents are represented by a page description language which is structured so that definition and declaratory commands are positioned only at the beginning of each distinct document segment. Each document has prologue sections, which contain definition and declaratory commands, and content portions which contain the specific tokens or commands for defining specific images. The definition and declaratory commands in the prologue sections of the document are arranged in a hierarchical tree so that each definition and declaratory command has a scope corresponding to the portion of the hierarchical tree subtended by that command. A structure processor handles resource declaration and definitions, dictionary generation, context declarations and references to data external to the document.