Patents Examined by Ulka J. Chauhan
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Patent number: 6753872Abstract: In a rendering processing system having a rendering memory for storing rendering pixel data generated by a rendering operation circuit and a display memory for storing the image data of a current frame read out from the rendering memory, the display memory stores only the pixel data read out from the rendering memory with prescribed information excluded therefrom. Thus, it is possible to decrease the storage capacity of the display memory and also reduce the time required for writing data into the display memory.Type: GrantFiled: January 9, 2001Date of Patent: June 22, 2004Assignee: Renesas Technology Corp.Inventors: Shohei Moriwaki, Yoshifumi Azekawa, Osamu Chiba, Kazuhiro Shimakawa
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Patent number: 6753870Abstract: A graphics system comprising a programmable sample buffer and a sample buffer interface. The sample buffer interface is configured to (a) buffer N streams of samples in N corresponding input buffers, wherein N is greater than or equal to two, (b) store N sets of context values corresponding to the N input buffers respectively, (c) terminate transfer of samples from a first of the input buffers to the programmable sample buffer, (d) selectively update a subset of state registers in the programmable sample buffer with context values corresponding to a next input buffer of the input buffers, (e) initiate transfer of samples from the next input buffer to the programmable sample buffer. The context values stored in the state registers of the programmable sample buffer determine the operation of an arithmetic logic unit internal to the programmable sample buffer on samples data.Type: GrantFiled: January 30, 2002Date of Patent: June 22, 2004Assignee: Sun Microsystems, Inc.Inventors: Michael F. Deering, Nathaniel David Naegle, Michael G. Lavelle
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Patent number: 6747654Abstract: A multiple device frame synchronization method and apparatus utilizes events completion signaling between multiple devices, such as multiple graphics processors. The signaling serves as a stall command for stalling graphics data rendering commands in a command FIFO of the rendering engine of a graphics processor in response to a rendering complete signal, or other event signal generated by the other graphics processor. Accordingly, the processor that, for example, completes a current frame relay is stalled until the other processor has completed its rendering function for a particular odd line, even line, entire frame or partial frame as desired.Type: GrantFiled: April 20, 2000Date of Patent: June 8, 2004Assignee: ATI International SRLInventors: Indra Laksono, Milivoje Aleksic
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Patent number: 6744439Abstract: A digital image processing circuit for replacing an input code associated with a pixel of the image with an output code selected in a first memory containing a set of codes, including an input bus for receiving the input code, an output bus for providing the output code, said first memory, means of address calculation of the first memory, means of address selection of the first memory between the input code and an address code generated by the address calculation means, a second memory for containing an address code generated by the address calculation means, and means of selection of the output code between a code read from the first memory and said code contained in the second memory.Type: GrantFiled: October 24, 2000Date of Patent: June 1, 2004Assignee: STMicroelectronics S.A.Inventors: Marc Laury, Franck Seigneret, Emmanuel Chiaruzzi, Philippe Monnier
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Patent number: 6744443Abstract: A method and apparatus employing lookup tables in a time sequential manner. A substrate has a display, a digital to analog converter, and a lookup table (LUT) formed thereon. The LUT is loaded with a LUT data set corresponding to an image subframe to be driven to the display. Successive LUT data sets corresponding to the next subframe are loaded after each subframe is driven to the display.Type: GrantFiled: November 19, 2001Date of Patent: June 1, 2004Assignee: Brillian CorporationInventors: Douglas J. McKnight, Douglas J. Gorny, Lowell F. Bohn, Jr.
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Patent number: 6741255Abstract: Apparatus, methods, systems and computer program products are disclosed that optimize the application of deferred image operations on a tiled source image. The invention dynamically creates a data structure (such as a directed acyclic graph (DAG)) representing the operations performed on various instances of one or more images to create a final image. The invention analyzes the data structure to determine which source image tiles are needed when the actual image data comprising the final image is required. Each of these tiles are then separately processed by all of the deferred operations to create the final image data. This approach reduces the number of times a tile is read into memory for processing and improves the performance of deferred image operations on a tiled source image.Type: GrantFiled: August 14, 1997Date of Patent: May 25, 2004Assignee: Sun Microsystems, Inc.Inventors: John L. Furlani, Alexandra R. Ohlson, Richard T. Inman
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Patent number: 6741253Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.Type: GrantFiled: October 9, 2001Date of Patent: May 25, 2004Assignee: Micron Technology, Inc.Inventors: William Radke, Atif Sarwari
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Method of implementing an accelerated graphics port for a multiple memory controller computer system
Patent number: 6741254Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: GrantFiled: November 27, 2000Date of Patent: May 25, 2004Assignee: Micron Technology, Inc.Inventor: Joseph Jeddeloh -
Patent number: 6741245Abstract: A method for decorating a virtual world model first builds a physical model from a plurality of building blocks. Each building block includes a microcontroller coupled to a plurality of connectors. The connectros are for physically and electronically connecting the blocks in a three-dimensional structure to form the model. An arrangement of the blocks in the model is derived by connecting the model to a host computer. The arrangement is expressed as a set of logical axioms. The set of logical axioms is processed by a logic program to identify large scale structural elements of the model, and decorative attributes are assigned to the large. scale structural elements.Type: GrantFiled: April 23, 1999Date of Patent: May 25, 2004Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Joseph W. Marks, David B. Anderson, James L. Frankel
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Patent number: 6734863Abstract: A display controller for a display apparatus having a memory function which can reduce power consumption efficiently is disclosed. A rewriting comparison circuit detects whether or not rewriting of different data by a graphic engine since the last display updating by a reflect control circuit, and stores resulting information into a TagRAM. The refresh control circuit checks the address of the TagRAM prior to the updating of the display and, only when the data at a corresponding address of a VRAM has been rewritten since the last display updating, the refresh control circuit performs reading in of the data from the VRAM and signaling of the data to the display apparatus having a memory function.Type: GrantFiled: March 30, 2000Date of Patent: May 11, 2004Assignee: NEC CorporationInventor: Takashi Ikeda
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Patent number: 6731290Abstract: Idle frames received by a graphics controller are compressed by evaluating two idle frames to create an encoding table used to replace selected pixel byte values in subsequent idle frames with codes. Possible pixel byte values are associated with a first set of counters, with each counter counting several different byte values as they occur with the first idle frame. A first subset of the possible pixel byte values is selected based on the counts in the first counters and each byte value in the first subset is associated with a second counter. The occurrences of the first subset of pixel byte values are counted in the second idle frame, and a second subset of pixel byte values is selected based on the counts in the second counters and used to create the encoding table. In one aspect, the encoding table is created when the second set of pixel byte values satisfy a threshold.Type: GrantFiled: September 28, 2001Date of Patent: May 4, 2004Assignee: Intel CorporationInventor: Ying Cui
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Patent number: 6731291Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.Type: GrantFiled: January 25, 2002Date of Patent: May 4, 2004Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Yasuhiro Nakatsuka, Keisuke Nakashima, Shigeru Matsuo, Masahisa Narita, Koyo Katsura, Hidehito Takewa, Tomoaki Aoki
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Patent number: 6731289Abstract: One aspect of the invention is a method for displaying extended range pixel values. The method includes the step of receiving a plurality of image pixel values each with at least one associated data value. The method also includes the steps of sending at least one of the plurality of image pixel values to a first display device (94) having a maximum display value; and sending at least one of the plurality of image pixel values exceeding maximum display value to a second display device (98). In a further embodiment, the at least one associated data value may be at least one of the group consisting of a pixel intensity, a color, and a location of the pixel value.Type: GrantFiled: May 12, 2000Date of Patent: May 4, 2004Assignee: Microsoft CorporationInventors: Mark S. Peercy, John M. Airey, Andrew D. Bowen
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Patent number: 6727907Abstract: A video data display board, device or method for inputting and displaying video data including vertical blanking interval data containing character data and other image data than the vertical blanking interval data. The video data display device has a data transfer circuit capable of transferring both of the data to devices different from each other, so that the processing of character information and image data are performed by using the different devices which perform an appropriate process according to the property of the data. The processed character and image data are displayed on a graphic display screen simultaneously.Type: GrantFiled: March 4, 2002Date of Patent: April 27, 2004Assignees: Renesas Technology Corp., Hitachi Video and Information System, Inc.Inventors: Itaru Nonomura, Yasuhiro Furukawa, Kazushige Hiroi, Akio Hayashi
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Patent number: 6717582Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.Type: GrantFiled: June 26, 2001Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventor: Joseph Jeddeloh
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Patent number: 6717583Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: GrantFiled: November 26, 2001Date of Patent: April 6, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Patent number: 6704021Abstract: A video graphics system (300) employs a method and apparatus for efficiently processing vertex information required to render graphics primitives requested for display by an application (313), such as a video game. The video graphics system includes a graphics driver (317), a graphics processor (305), a memory component (309, 321) that is accessible by the graphics processor, and a memory component (319) that is inaccessible by the graphics processor. After receiving, from the application, a drawing command that includes vertex indices and a reference to a vertex buffer (325) stored in the graphics processor-inaccessible memory component, the graphics driver allocates a new temporary vertex buffer (327) in the graphics processor-accessible memory component and copies the contents of the graphics processor-inaccessible vertex buffer into the temporary vertex buffer.Type: GrantFiled: November 20, 2000Date of Patent: March 9, 2004Assignee: ATI International SRLInventors: Philip J. Rogers, Matthew P. Radecki
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Patent number: 6700579Abstract: Digital video processing apparatus comprises: a plurality of render processors arranged in an operational sequence, each operable to render an output result relating to an image of a video signal from input data relating to that and/or other images received from a preceding render processor in the operational sequence; each render processor being operable to detect and communicate to other render processors whether its rendered output is constant between adjacent images.Type: GrantFiled: July 28, 1999Date of Patent: March 2, 2004Assignee: Sony United Kingdom LimitedInventor: Antony James Gould
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Patent number: 6697074Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.Type: GrantFiled: July 30, 2002Date of Patent: February 24, 2004Assignee: Nintendo Co., Ltd.Inventors: Vimal Parikh, Robert Moore, Howard Cheng
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Patent number: 6693640Abstract: An image processing apparatus is composed of a plurality of function processing units for performing image processing, a high priority function selection part for selecting functions, execution of each of which is required by a corresponding one of the function processing units, based on the predetermined priority for each of the functions; and a data control unit including a data transfer part for preferentially accessing the shared memory which the function selected by the high priority function selection part requires, and a plurality of data holding parts, each of the data holding parts holding a predetermined amount of data transmitted with each of the plurality of function processing units, wherein the data transfer part controls the bus connecting the CPU and the shared memory based on requirement sent from each of the function processing units, and each of the plurality of function processing units transmits data with the data control unit separately from the others of the plurality of function procesType: GrantFiled: April 4, 2002Date of Patent: February 17, 2004Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Shoji Muramatsu, Yoshiki Kobayashi, Kenji Hirose, Shigetoshi Sakimura