Abstract: A monocular input image is transformed to give it an enhanced three dimensional appearance by creating at least two output images. Foreground and background objects are segmented in the input image and transformed differently from each other, so that the foreground objects appear to stand out from the background. Given a sequence of input images, the foreground objects will appear to move differently from the background objects in the output images.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

Abstract: An apparatus comprises two or more image processing units and a main merger unit. Each image processing unit comprises four information processing units and a sub merger unit for merging data output from the four information processing units. The main merger unit merges data output from multiple sub merger units. Data output from the information processing units are stored in parallel in a register on a unit length basis for serial transmission. Auxiliary data is added for identifying data that have been altered or modified. The serial data, with the auxiliary data added thereto, are output to the main merger unit.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. An application program requiring graphics to be rendered is coded to bound a sequence of calls to basic rendering functions, defining a desired image to be rendered, between begin-program and end-program identifiers. When the application program is executed on a host operating system, a begin-program identifier invokes a function in a graphics device driver in the host system. The function captures the calls to the rendering functions within the application program in a memory as hardware instructions to the graphics subsystem. When the function encounters an end-program identifier, it registers the captured hardware instructions with the host system as an executable program.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises apparatus for detecting one or more video underflow conditions. The raster engine includes a first in first out (FIFO) memory, which obtains video data from a frame buffer and provides video data to a video pipeline, along with input and output counters associated with the FIFO memory. A control logic system is associated with the FIFO memory and adapted to provide an underflow indication according to the input and output counter values. A method for detecting video underflow in a video controller raster engine is also disclosed.

Abstract: A pixel is textured by storing a first texel reference value, a second texel reference value, and texel mapping values where each texel mapping value represents a k-tuple of (ternary) references to the first texel reference value, the second texel reference value and a third texel reference value to thereby represent a block of texels. A pixel value for the pixel is generated from the stored texel values and the pixel is displayed responsive to the generated pixel value. In some embodiments, respective pluralities of texel reference values and texel mapping values that map thereto are stored for respective ones of a plurality of overlapping blocks of texels. In further embodiments, a first mipmap value for a pixel is bilinearly interpolated from the retrieved texel values for the set of nearest neighbor texels. A second mipmap value for the pixel is generated by averaging the retrieved texel values for the set of nearest neighbor texels.

Abstract: A non-blocking cache for texture mapping is implemented by separating Cache Tags from Cache Data. Multiple requests for data may be processed in parallel without strict ordering or synchronization. Separating Cache Tags and Cache Data results in a texture memory cache design that preempts stalling which would otherwise occur in case of cache-misses. Multiple Cache Tags with corresponding respective system memory controllers and Data Cache units allow for simultaneous processing of multiple requests without strict ordering. In preferred embodiments the texture memory cache may also be configured to predict cache misses and merge with burst reads from memory, and may equally be configured to minimize memory read-requests necessary during multitexturing, thus maximizing bandwidth.

Abstract: A processing device (200) includes three hardware extensions: a motion estimation extension 202, a pixel interpolation extension 204 and a DCT/iDCT extension 206. The hardware extensions perform functions which would otherwise be highly processor intensive, resulting in high power consumption and/or low quality video/imaging processing. The processing device 200 could be used, for example, in a mobile videophone 150.

Abstract: A sample filtering system and method for concurrently filtering sample data for two or more sequential pixels (in a scan-line) are disclosed. The system may include a sample cache, a control register, a read cache controller, and a sample-to-pixel calculation unit. The read cache controller reads a first set of S samples from the sample cache, and outputs a second set of S samples to the sample-to-pixel calculation unit. The second set of samples may have one or more subsets of samples, with each subset of samples selected to cover the filter region for one of the sequential pixels. The sample-to-pixel calculation unit may process each subset separately and concurrently.

Abstract: An apparatus for processing image data to produce an image for covering an image area of a display includes a plurality of graphics processors, each graphics processor being operable to render the image data into frame image data and to store the frame image data in a respective local frame buffer; a control processor operable to provide instructions to the plurality of graphics processors; and at least one merge unit operable to synchronously receive the frame image data from the respective local frame buffers and to synchronously produce combined frame image data based thereon.

Abstract: A circuit for outputting area pattern bits from an area pattern array. The circuit includes a first stage, second stage and third stage. The first stage is configured to output N adjacent scan lines from a 2N×2N area pattern array based on a first address. N is a positive integer. The second stage is configured to receive the N adjacent scanlines and to select an N×N block from the N adjacent scanlines based on a second address. The third stage is configured to (a) select an (N/2)×N region of bits from the N×N block and load bits of the (N/2)×N region into a set of pixel tag outputs in a first mode, and (b) select an N×(N/2) region of bits from the N×N block and load bits of the N×(N/2) region into the set of pixel tag outputs in a second mode.

Abstract: A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported L1 texture cache local to its 2D/3D pipeline that is backed by the relatively large, single ported portion of the shared cache. Leveraging the shared cache as a secondary level texture cache reduces system memory bandwidth and die size without significant sacrifice in performance.

Abstract: An embodiment of a graphics device that maintains load balance on a graphics bus when an upgrade graphics device is installed is disclosed. The embodiment includes load balancing buffers for the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB# on a 2X mode AGP graphics device. The load balancing buffers couple the 2X mode AGP graphics device to the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB#, but the load balancing buffers are not connected to any internal circuits within the 2X mode AGP graphics device. The load balancing buffers provide equal capacitive loading between the strobe signals AD_STB0 , AD_STB1 , and SB_STB and their compliment signals AD_STB0#, AD_STB1#, and SB_STB# when an upgrade 4X mode AGP graphics device is installed.

Abstract: A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.

Abstract: A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.

Abstract: A data buffering apparatus comprises a plurality of sessions and buffer logic. The plurality of session are respectively associated with session identifiers. Each of the sessions is configured to identify entries in a queue having the session's associated identifier and to pull, from the queue, the identified entries. Each of the sessions is further configured to retrieve data from the buffers pointed to by the identified entries that have the session's associated identifier. The buffer logic is configured to store a set of data to one of a plurality of buffers. The buffer logic is further configured to store, in the queue, for each expected retrieval of the set of data from the one buffer by the sessions, an entry that points to the one buffer and has a different session identifier associated with a different one of the sessions.

Abstract: Tile buffers in a graphics processing system are managed use “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified. Two memory spaces store tile data, and two logical buffers are used to access the memory spaces. For each tile, a tile association is maintained, indicating which of the two memory spaces is associated with each of the two logical buffers. To copy a tile of the first logical buffer to the second logical buffer, the tile association for the tile being copied is modified. Data for a tile is written to the memory space associated with a target logical buffer after ensuring that the tile association for the tile associates the target logical buffer with a different one of the two memory spaces from the other logical buffer.

Abstract: Tile data for drawing and desktop buffers in a desktop compositor system is managed using “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified. For each tile in drawing buffers and desktop buffers, an association is maintained with a location in a tile memory, and the number of buffer tiles associated with each location is tracked. To copy a tile from one buffer to another, the tile association for the tile in the destination buffer is modified. New data for a tile of a buffer is written to the tile memory location associated with the buffer after ensuring that the tile memory location is not associated with any other tiles of any of the buffers. As a result, memory bandwidth can be considerably reduced.