Abstract: A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a portion of a shader program and selects a first set of fragments to be processed. Subsequent sequences of instructions are converted until all of the instructions comprising the shader program have been executed on the first set of fragments. Each remaining set of fragments is processed by the shader program until all of the fragments are processed in the same manner. Furthermore, the instructions can contain one or more loop or branch program instructions that are conditionally executed. Additionally, when instructions within a loop as defined by a loop instruction are being executed a current loop count is pipelined through the programmable graphics shader and used as an index to access graphics memory.

Abstract: A system and process for reconstructing optimal texture maps from multiple views of a scene is described. In essence, this reconstruction is based on the optimal synthesis of textures from multiple sources. This is generally accomplished using basic image processing theory to derive the correct weights for blending the multiple views. Namely, the steps of reconstructing, warping, prefiltering, and resampling are followed in order to warp reference textures to a desired location, and to compute spatially-variant weights for optimal blending. These weights take into consideration the anisotropy in the texture projection and changes in sampling frequency due to foreshortening. The weights are combined and the computation of the optimal texture is treated as a restoration problem, which involves solving a linear system of equations.

Abstract: A graphics system and method for storing and accessing texture maps comprising texels. The graphics system may include a graphics processor and a texture memory comprising a plurality of memory devices for storing the texture maps. The texels (or portions of the texels) may be stored in the memory devices in an interleaved fashion. The texel data is interleaved in the memory devices to guarantee that, no matter which N×M array of texels is accessed, each texel in the array is present in a different memory device or chip and hence are concurrently available. Thus the N×M array of texels may be output concurrently or simultaneously, regardless of which array is accessed, i.e., regardless of which pixel is addressed. Embodiments are also described where the memory devices output arrays of texels for at least two respective neighboring pixels, or a 3D array of texels, in parallel in response to a single read transaction.

Abstract: A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.

Abstract: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

Abstract: A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.

Abstract: In accordance with a first mode of operation of the present invention, a portrait image is received from a system device. The portrait image is translated and stored within the graphics engine memory such that it can be displayed on a landscape monitor that has been rotated 90 degrees. Likewise, when portrait data stored within the memory is sent to the system it is translated such that it is sent back in the same format received by the system. In a second mode of operation in accordance with the present invention, a landscape image received by the graphics adapter is stored in the graphics adapter memory without any translation.

Abstract: A graphics subsystem having a programmable shader controllable by both state-based control information, such as DirectX 8 control information, and program instructions, such as DirectX 9 shader program instructions. The programmable shader translates state-based control information received from a host computer into native control information. The programmable shader translates into native control information program instructions fetched from memory locations identified by a received memory reference and program instructions received from the graphics subsystem. Native control information configures computation units of the programmable shader. The programmable shader optimizes the generated native control information by combining certain operations. The graphics subsystem detects memory references sent from the host computer and pre-fetches program instructions for transmission to the programmable shader.

Abstract: A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame.

Abstract: A highly integrated multimedia processor employs a shared cache between tightly coupled central processing and graphics units to provide the graphics unit access to data retrieved from system memory or data processed by the central processing unit before the data is written-back or written-through to system memory, thus reducing system memory bandwidth requirements. Regions in the shared cache can also be selectively locked down thereby disabling eviction or invalidation of a selected region, to provide the graphics unit with a local scratchpad area for applications such as, but not limited to, temporary video line buffering storage for filter applications and composite buffering for blending texture maps in multi-pass rendering.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.

Abstract: A vertex data access apparatus and method. The apparatus receives a vertex index, compares the vertex index with any vertices' indices used before, issues a request if necessary for fetching vertex data in system memory, stores the return vertex data in a vertex data queue and gets corresponding vertex data from the vertex data queue for further processing and, more particularly, if the vertex index is the same as one of those vertices' indices, the corresponding vertex data can be directly fetched from the vertex data queue. The vertex data queue performs the vertex cache function.

Abstract: Digital video processing apparatus comprising: a plurality of render processors arranged in an operational sequence, each operable to render an output result relating to an image of a video signal from input data relating to that and/or other images received from a preceding render processor in the operational sequence; and a render controller for controlling rendering operation of the render processors; each render processor being operable to communicate dependency data to the render controller, indicating which images must be rendered by a preceding render processor in order for that render processor to render output data relating to a required image; and the render controller being operable to control operation of the render processors so that images required by each render processor are rendered by preceding render processors in the operational sequence.

Abstract: A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

Abstract: Image data are obtained from a recording medium, and dummy image data are generated based on the obtained image data. It is possible to switch between image displayed based on the generated dummy image data, and image data directly displayed based on the obtained image data. As a result, the dummy image may be displayed when a third party is near. Furthermore, the displayed dummy image can be used for editing, and the edited image may be printed.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Abstract: A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.

Abstract: A system and method are provided for executing a cellular automata program in a hardware graphics pipeline. Initially, cell values are received in a hardware graphics pipeline. Next, the cell values are rendered to generate a condition value utilizing the hardware graphics pipeline. A cell value result for the subsequent generation is read from a rule map according to the condition value utilizing the hardware graphics pipeline. Still yet, additional cell values are stored based on the rule map value.