Abstract: A method for updating an integrated display frame buffer of a display module in a mobile electronic device, comprising a local frame buffer and a processor, comprising the steps of transferring display information to said local frame buffer, updating said display frame buffer by transferring said display information from said local frame buffer to said display frame buffer, and displaying said display information on said display module. Furthermore, the invention comprises the additional steps of detecting changes of said display information stored in said local frame buffer, and updating said display frame buffer when a change of said display information in said local frame buffer is detected.

Abstract: A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.

Abstract: A system and method for managing power consumption of an information handling system dynamically switches between high and low clock speed data transfers with double data rate (DDR) memory. The selection of a high clock speed dynamically switches the DDR memory to connect to a parallel termination for more rapid data transfers with increased power consumption. The selection of a low clock speed dynamically switches the DDR memory to disconnect the parallel termination for slower data transfers with reduced power consumption. In one embodiment, portable computer graphics DDR memory reduces power consumption by selecting low clock speed transfers without parallel termination when operating on internal power. The portable computer graphics DDR memory provides improved display resolution by selecting high clock speed transfers with parallel termination when operating on external power or when displaying information from high resolution applications.

Abstract: A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.

Abstract: A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.

Abstract: The present invention is broadly directed to a system of components defining a plurality of nodes and a random access memory (RAM) connected to each node. The system comprises at least one producer functional unit configured to perform a predetermined processing function resulting in the creation of at least one producer message, a communication mechanism configured to manage and control communication of messages with other nodes, at least one pointer that is configurable to point to a storage location within the RAM, and a message logic configured to interpret content of the at least one producer message, the message logic further configured to associate the producer message with a subset of the at least one pointers based upon the content of the at least one producer message, the message logic further configured to store the at least one producer message within the RAM at the locations indicated by the associated subset of at least one pointer.

Abstract: A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.

Abstract: An image processing system processes image data in response to a sequence of image processing steps defined by a process tree data structure. The process tree comprises a plurality of interconnected nodes, including input nodes and at least one output node. Output rendering is performed a frame at a time, and each frame is rendered in a time determined by the amount of processing defined by the process tree. The process tree may comprise many branches of interconnected nodes, and the user can selectively cache intermediately rendered frames at nodes where the contributing process tree branches are relatively stable in their configuration. The user may then make modifications to processes in other parts of the process tree, without having to wait for image data to be rendered from unchanged parts of the process tree.

Abstract: A method and apparatus for generating depth values in a programmable graphics system. Depth values are calculated under control of a pixel program using a variety of sources as inputs to programmable computation units (PCUs) in the programmable graphics systems. The PCUs are used to compute traditional interpolated depth values and modified depth values. Th PCUs are also used to compute arbitrary depth values which, unlike traditional interpolated depth values and modified depth values, are not dependent on the coordinates of the geometry primitive with which the arbitrary depth values are associated. Several sources are available as inputs to the PCUs. Clipping with optional clamping is performed using either interpolated depth values or calculated depth values, where calculated depth values are arbitrary depth values or modified depth values. Final depth values, used for depth testing, are selected from interpolated depth values and arbitrary depth values after clipping is performed.

Abstract: A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.

Abstract: In accordance with the present invention, a write behind controller receives control information from a display device controller in order to determine a current location available in a frame buffer for receiving information. Write accesses of the frame buffer by a rendering engine are prohibited if the access is to an area below a currently available location of the frame buffer. Generally, the rendering engine will be stalled when the requested address location has not yet displayed its data. Subsequently, the write access to the frame buffer is allowed when location has been rastered.

Abstract: An apparatus for scalable image processing includes a display, multiple graphics functional units and a mode selector. Each of the graphics functional units has a configuration of a predetermined type to control the display. The mode selector determines which combination of graphics functional units controls the display. A method for scalable image processing includes monitoring at least one parameter, determining whether to switch from one graphics functional unit configuration to a new graphics functional unit configuration based upon one or more of the parameters, and switching to the new graphics functional unit configuration.

Abstract: A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has a variable width input and output. The variable width on the input side facilitates the reception and storage of loosely packed data. The variable width output allows for the single-cycle output of multi-word data. Packing of the data occurs on the write-side of the FIFO structure.

Abstract: A system, method and computer program product are provided for branching during programmable processing in a computer graphics pipeline. Initially, data is received. Programmable operations are then performed on the data in order to generate output. Such operations are programmable by a user utilizing instructions from a predetermined instruction set. When performing the programmable operations in the foregoing manner, programmable branching may take place between the programmable operations. Subsequently, the output is stored in memory. Also included is a system, method and computer program product for directly executing a function in the computer graphics pipeline. Initially, input data is received in the computer graphics pipeline. A mathematical function is directly performed on the input data in order to generate output data. It should be noted that the mathematical function is directly performed in the computer graphics pipeline without a texture look-up or aid from a central processing unit.

Abstract: A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.

Abstract: A feedback path to the processor for a video signal in a computer. The video image data is not normally subjected to benchmark testing because it would make it susceptible to illegal copying. The digital video output signal is sent back to the processor one pixel at a time, with a delay between pixels equivalent to one line time. The result is that the pixel feed is so slow that digital copying is impractical. A lockout timer allows the pixel data to be sent to the processor only at intervals.

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: In accordance with a specific implementation of the present invention, the control portion of a graphics processor receives a command having both a data portion and a data duration portion. When the data duration portion indicates the data is transient data for short-term use, the control portion stores the data associated with the data portion at the first memory partition. When the data duration portion indicates the data is persistent data for long-term use, the control portion stores the data associated with the data portion at a second memory partition. In a multiple processor system, transient data may be stored only in a memory partition associated with a first processor, while persistent data may be stored in multiple memory partitions, one for each graphics processor.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.