Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

Abstract: An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.

Abstract: A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.

Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.

Abstract: Methods, systems, and devices related to techniques for saturating a host interface are described. A set of data stored at a first memory device may be communicated over an interface during a read operation performed in response to receiving a read request associated with the set of data. A control component may determine if the interface entered an idle state during portions of the read operation. Based on detecting an idle state of the interface, the control component may transfer the set of data from the first memory device to a second memory device. After receiving a second read request for the set of data, the memory device may access the set of data from the second memory device and communicate the set of data over the interface, where the interface may remain in a saturated state throughout the second read operation.

Abstract: The present disclosure provides a detection circuit, including: a generation unit provided with a plurality of output terminals and configured to generate random detection data and output one bit of the random detection data through each output terminal; a first drive unit provided with a plurality of first input terminals connected to the plurality of output terminals of the generation unit in one-to-one correspondence and a plurality of output terminals connected to a memory array, and configured to transmit the random detection data to the memory array, wherein the memory array is configured to store the random detection data; and a comparison unit provided with a plurality of first input terminals connected to the plurality of output terminals of the generation unit in one-to-one correspondence and a plurality of second input terminals connected to the memory array.

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined source line voltage to the source line of selected ones of the memory holes in a predetermined grouping and a read level voltage to at least one of the word lines associated with the predetermined grouping. The control means counts the memory cells conducting during each of a first and a second read operation and adjusts the predetermined source line voltage accordingly.

Abstract: A memory system to generate data with a relation among data groups for reliably storing a predetermined number of bits per memory cell in memory cells. For example, from first groups of date bits, a second group of data bits is generated. Data groups of the predetermined number is formed to have the first groups and the second group and a predetermined relation (e.g., XOR or XNOR) among the data groups. Threshold levels of memory cells in a memory cell group are determined based on a predetermined mapping, where a threshold level of each memory cell is determined to represent one bit from each of the data groups. In the predetermined mapping, bit values represented by any two successive threshold levels differ by one bit. Threshold voltages in the memory cell group are programmed according to the threshold levels to store the data groups with improved reliability.

Abstract: A memory device includes a plurality of pages arranged in columns, each page is constituted by a plurality of memory cells arranged in rows on a substrate, the memory cells included in the page are memory cells of a plurality of semiconductor base materials that stand on the substrate in a vertical direction or that extend in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, a

Abstract: Respective values of a subset of the plurality of memory cells of a memory device are compared to a pattern of pre-programmed memory cells. The pattern pre-programmed memory cells comprise representations of values of the pattern of pre-programmed memory cells when a temperature criterion is satisfied. Responsive to determining that at least a threshold number of the respective values of the subset matches the pattern of pre-programmed memory cells, a temperature reading from a thermal sensor coupled to the memory device is identified. Responsive to determining that the temperature reading does not correspond to a temperature criterion, determining that the thermal sensor has failed.

Abstract: Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

Abstract: A memory circuit includes a first programming device, a first circuit branch and a second circuit branch. The first programming device includes a first control terminal coupled to a first word line, and a first connecting end. The first circuit branch includes a first diode, and a first fuse element coupled to the first diode. The second circuit branch includes a second diode, and a second fuse element coupled to the second diode. The first circuit branch and the second circuit branch are coupled to the first connecting end of the first programming device.

Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes one or more programming pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective programming levels of a plurality of programming levels as part of the program operation. Responsive to the one or more programming pulses being applied, the control logic further performs a program verify operation to verify whether the memory cell in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.

Abstract: In one embodiment, a memory system receives a request to perform a memory access operation, the request identifying a memory cell in a segment of the memory system comprising at least a portion of the memory device. The system determines that an operating temperature of the memory device satisfies a threshold criterion. Responsive to determining that the operating temperature of the memory device satisfies the threshold criterion, the system determines a temperature compensation value corresponding to an access control voltage adjustment value specific to the segment of the memory system. The system adjusts, based on an amount represented by the temperature compensation value, an access control voltage applied to the memory cell during the memory access operation.

Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output.